mainboard: Add MSI MS-7707
* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) * SandyBridge Intel P67 (BD82x6x) * Winbond 25Q32BV (4MB) * Fintek F71808A * Intel 82579V Gigabit * NEC uPD720200 USB 3.0 Host Controller * IME 7.0.4.1197 Working: * PCIe gfx adapter * PS/2 Keyboard * USB3.0 * Ethernet * S0/S3/S5 * HWM Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3 Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Max Blau
Felix Held
parent
13bfd04a99
commit
517eda5ca4
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@ -0,0 +1,57 @@
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if BOARD_MSI_MS7707
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_FINTEK_F71808A
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select BOARD_ROMSIZE_KB_4096
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_RESUME
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select MAINBOARD_USES_IFD_GBE_REGION
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select NO_UART_ON_SUPERIO
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select SERIRQ_CONTINUOUS_MODE
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config MAINBOARD_DIR
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string
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default msi/ms7707
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config MAINBOARD_PART_NUMBER
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string
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default "MS-7707"
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x7707
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1462
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config DRAM_RESET_GATE_GPIO
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int
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default 60
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX # FIXME: check this
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int
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default 2
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config CBFS_SIZE
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hex
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default 0x200000
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config VGA_BIOS_FILE
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string
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default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vgabios.bin"
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config VGA_BIOS_ID
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string
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default "8086,0102"
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endif
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@ -0,0 +1,2 @@
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config BOARD_MSI_MS7707
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bool "MS-7707"
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@ -0,0 +1 @@
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romstage-y += gpio.c
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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}
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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Category: desktop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2011
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@ -0,0 +1,117 @@
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chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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register "gfx.link_frequency_270_mhz" = "0"
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register "gfx.ndid" = "3"
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device cpu_cluster 0x0 on
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0x0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0x0 on
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subsystemid 0x1462 0x7707 inherit
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x000c0291"
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register "gen2_dec" = "0x000c0a01"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x33"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "gpe0_en" = "0x28000040"
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on end # Intel Gigabit Ethernet
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio Audio controller
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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chip superio/fintek/f71808a
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register "multi_function_register_0" = "0x00" # 0x28
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register "multi_function_register_1" = "0xc0" # 0x29
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register "multi_function_register_2" = "0x20" # 0x2a
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register "multi_function_register_3" = "0x4f" # 0x2b
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register "multi_function_register_4" = "0x90" # 0x2c
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register "hwm_peci_tsi_ctrl" = "0x02" # 0x0a - PECI enabled, 1.23 V
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register "hwm_tcc_temp" = "0x64" # 0x0c - TCC temperature = 100 °C
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register "hwm_fan1_seg1_speed" = "0xff" # 0xaa - Fan 1 segment 1
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register "hwm_fan1_seg2_speed" = "0xe2" # 0xab - Fan 1 segment 2
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register "hwm_fan1_seg3_speed" = "0xaf" # 0xac - Fan 1 segment 3
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register "hwm_fan1_seg4_speed" = "0x89" # 0xad - Fan 1 segment 4
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register "hwm_fan1_seg5_speed" = "0x72" # 0xae - Fan 1 segment 5
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register "hwm_fan1_temp_src" = "0x10" # 0xaf - Fan 1 source = PECI
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register "hwm_fan2_seg1_speed" = "0xff" # 0xba - Fan 2 segment 1 = 100%
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register "hwm_fan2_seg2_speed" = "0xd9" # 0xbb - Fan 2 segment 2 = 86%
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register "hwm_fan2_seg3_speed" = "0xb2" # 0xbc - Fan 2 segment 3 = 74%
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register "hwm_fan2_seg4_speed" = "0x99" # 0xbd - Fan 2 segment 4 = 62%
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register "hwm_fan2_seg5_speed" = "0x80" # 0xbe - Fan 2 segment 5 = 50%
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register "hwm_fan2_temp_src" = "0x1e" # 0xbf - Fan 2 source = temperature 2
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register "hwm_domain1_en" = "0x01"
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register "hwm_fan1_boundary_hysteresis" = "0x43"
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register "hwm_vt1_boundary_1_temperature" = "0x52" # 82°C
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register "hwm_vt1_boundary_2_temperature" = "0x46" # 70°C
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register "hwm_vt1_boundary_3_temperature" = "0x41" # 65°C
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register "hwm_vt1_boundary_4_temperature" = "0x37" # 55°C
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device pnp 4e.1 off end # Serial Port
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device pnp 4e.4 on # Hardware monitor
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io 0x60 = 0x295
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irq 0x70 = 0
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# global
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irq 0x27 = 0x10 # PWOK follows Intel sequence
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irq 0x2d = 0x2e # Anykey+MouseButton wakeup
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end
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device pnp 4e.5 on # Keyboard
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io 0x60 = 0x060
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 4e.6 on # GPIO
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irq 0x70 = 0
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irq 0xd0 = 0x20 # GPIO2 Output Enable
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irq 0xd1 = 0x20 # GPIO2 Output Data
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irq 0xd3 = 0x20 # GPIO2 Drive Enable
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end
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device pnp 4e.7 off # WDT
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io 0x60 = 0xa00
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end
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device pnp 4e.8 off end # CIR
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device pnp 4e.a on # PME, ACPI, Power Saving Registers
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irq 0xe2 = 0x0c # EuP control
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irq 0xed = 0xc0 # EuP Watchdog Control
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irq 0xf4 = 0x10 # Keep Last State Select
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irq 0xf9 = 0x09 # LED VSB Mode Select
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end
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 off end # Internal graphics
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end
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end
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@ -0,0 +1,41 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, // DSDT revision: ACPI 2.0 and up
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 // OEM revision
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)
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{
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/* Some generic macros */
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/bd82x6x/acpi/platform.asl>
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/* global NVS and variables. */
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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}
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}
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@ -0,0 +1,189 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; version 2 of
|
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* the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
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*/
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_NATIVE,
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.gpio3 = GPIO_MODE_NATIVE,
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.gpio4 = GPIO_MODE_NATIVE,
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.gpio5 = GPIO_MODE_NATIVE,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_NATIVE,
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.gpio12 = GPIO_MODE_NATIVE,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_NATIVE,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_GPIO,
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.gpio21 = GPIO_MODE_NATIVE,
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.gpio22 = GPIO_MODE_NATIVE,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio16 = GPIO_DIR_INPUT,
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.gpio17 = GPIO_DIR_INPUT,
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.gpio20 = GPIO_DIR_OUTPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_INPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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.gpio31 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio8 = GPIO_LEVEL_HIGH,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio20 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_HIGH,
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.gpio29 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_reset = {};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_GPIO,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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||||
.gpio35 = GPIO_MODE_NATIVE,
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.gpio36 = GPIO_MODE_NATIVE,
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.gpio37 = GPIO_MODE_NATIVE,
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.gpio38 = GPIO_MODE_NATIVE,
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||||
.gpio39 = GPIO_MODE_NATIVE,
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||||
.gpio40 = GPIO_MODE_NATIVE,
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||||
.gpio41 = GPIO_MODE_NATIVE,
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.gpio42 = GPIO_MODE_NATIVE,
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.gpio43 = GPIO_MODE_NATIVE,
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.gpio44 = GPIO_MODE_NATIVE,
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.gpio45 = GPIO_MODE_GPIO,
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.gpio46 = GPIO_MODE_NATIVE,
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.gpio47 = GPIO_MODE_NATIVE,
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.gpio48 = GPIO_MODE_NATIVE,
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.gpio49 = GPIO_MODE_GPIO,
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.gpio50 = GPIO_MODE_NATIVE,
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.gpio51 = GPIO_MODE_NATIVE,
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.gpio52 = GPIO_MODE_NATIVE,
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.gpio53 = GPIO_MODE_NATIVE,
|
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.gpio54 = GPIO_MODE_NATIVE,
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.gpio55 = GPIO_MODE_NATIVE,
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.gpio56 = GPIO_MODE_NATIVE,
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.gpio57 = GPIO_MODE_GPIO,
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.gpio58 = GPIO_MODE_NATIVE,
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.gpio59 = GPIO_MODE_NATIVE,
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.gpio60 = GPIO_MODE_NATIVE,
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.gpio61 = GPIO_MODE_NATIVE,
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.gpio62 = GPIO_MODE_NATIVE,
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.gpio63 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_OUTPUT,
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.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio45 = GPIO_DIR_OUTPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio45 = GPIO_LEVEL_HIGH,
|
||||
.gpio57 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0887, /* Codec Vendor / Device ID: Realtek */
|
||||
0x14627707, /* Subsystem ID */
|
||||
|
||||
0x0000000f, /* Number of 4 dword sets */
|
||||
/* NID 0x01: Subsystem ID. */
|
||||
AZALIA_SUBVENDOR(0x0, 0x14627707),
|
||||
|
||||
/* NID 0x11. */
|
||||
AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0),
|
||||
|
||||
/* NID 0x12. */
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
|
||||
|
||||
/* NID 0x14. */
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x01014410),
|
||||
|
||||
/* NID 0x15. */
|
||||
AZALIA_PIN_CFG(0x0, 0x15, 0x01011412),
|
||||
|
||||
/* NID 0x16. */
|
||||
AZALIA_PIN_CFG(0x0, 0x16, 0x01016411),
|
||||
|
||||
/* NID 0x17. */
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x01012414),
|
||||
|
||||
/* NID 0x18. */
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x01813c40),
|
||||
|
||||
/* NID 0x19. */
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50),
|
||||
|
||||
/* NID 0x1a. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),
|
||||
|
||||
/* NID 0x1b. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20),
|
||||
|
||||
/* NID 0x1c. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
|
||||
|
||||
/* NID 0x1d. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0),
|
||||
|
||||
/* NID 0x1e. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x01454130),
|
||||
|
||||
/* NID 0x1f. */
|
||||
AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/common/pmbase.h>
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
/* IO Decode Ranges Register */
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
|
||||
/* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400);
|
||||
|
||||
u16 reg16;
|
||||
reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);
|
||||
reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16);
|
||||
}
|
||||
|
||||
void mainboard_rcba_config(void)
|
||||
{
|
||||
}
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{1, 0, 0},
|
||||
{1, 0, 0},
|
||||
{1, 0, 1},
|
||||
{1, 0, 1},
|
||||
{1, 0, 2},
|
||||
{1, 0, 2},
|
||||
{1, 0, 3},
|
||||
{1, 0, 3},
|
||||
{1, 0, 4},
|
||||
{1, 0, 4},
|
||||
{1, 0, 6},
|
||||
{1, 0, 5},
|
||||
{1, 0, 5},
|
||||
{1, 0, 6},
|
||||
};
|
||||
|
||||
void mainboard_early_init(int s3resume)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_config_superio(void)
|
||||
{
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[2], 0x52, id_only);
|
||||
}
|
||||
Loading…
Reference in New Issue