Intel Sandy Bridge: udelay.c: Change comparison from <= to <

Currently code in `udelay.c` differs between the Intel northbridges
GM45, 945 on the one hand and Sandy Bridge on the other hand.

The reason for this is that a wrong comparison > was used.

The following commit

    commit 784ffb3db6
    Author: Sven Schnelle <svens@stackframe.org>
    Date:   Tue Jan 10 12:16:38 2012 +0100

        i945: fix tsc udelay()

        Reviewed-on: http://review.coreboot.org/530

fixed the sign from > to <, whereas Stefan Reinauer changed it from
> to <= before adding the Sandy Bridge port in the following commit.

    commit 00636b0dae
    Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Date:   Wed Apr 4 00:08:51 2012 +0200

        Add support for Intel Sandybridge CPU (northbridge part)

        Reviewed-on: http://review.coreboot.org/854

As there are no technical reasons for this difference, unify this
between the chipsets. See the discussion of the other patch set in
Gerrit [1].

[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c

Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3259
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>

src/northbridge/intel/sandybridge/udelay.c

@@ -64,5 +64,5 @@ void udelay(u32 us)
 	do {
 		tsc = rdtsc();
 	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
 }