mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Device(AAHB) {
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Name(_HID,"AAHB0000")
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Name(_UID,0x0)
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Name(_CRS, ResourceTemplate()
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{
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IRQ(Edge, ActiveHigh, Exclusive) {7}
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Memory32Fixed(ReadWrite, 0xFEDC0000, 0x2000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(GPIO) {
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Name (_HID, "AMD0030")
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Name (_CID, "AMD0030")
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Name(_UID, 0)
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Name(_CRS, ResourceTemplate() {
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(FUR0) {
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Name(_HID,"AMD0020")
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Name(_UID,0x0)
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Name(_CRS, ResourceTemplate() {
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IRQ(Edge, ActiveHigh, Exclusive) {10}
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Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(FUR1) {
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Name(_HID,"AMD0020")
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Name(_UID,0x1)
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Name(_CRS, ResourceTemplate() {
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IRQ(Edge, ActiveHigh, Exclusive) {11}
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Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(I2CA) {
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Name(_HID,"AMD0010")
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Name(_UID,0x0)
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Name(_CRS, ResourceTemplate() {
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IRQ(Edge, ActiveHigh, Exclusive) {3}
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Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(I2CB)
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{
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Name(_HID,"AMD0010")
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Name(_UID,0x1)
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Name(_CRS, ResourceTemplate() {
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IRQ(Edge, ActiveHigh, Exclusive) {15}
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Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(I2CC) {
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Name(_HID,"AMD0010")
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Name(_UID,0x0)
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Name(_CRS, ResourceTemplate() {
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IRQ(Edge, ActiveHigh, Exclusive) {6}
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Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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Device(I2CD)
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{
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Name(_HID,"AMD0010")
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Name(_UID,0x1)
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Name(_CRS, ResourceTemplate() {
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IRQ(Edge, ActiveHigh, Exclusive) {14}
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Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)
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})
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Method (_STA, 0x0, NotSerialized) {
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Return (0x0F)
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}
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}
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@ -73,7 +73,7 @@ DefinitionBlock (
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#include <pci_int.asl>
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#include <pci_int.asl>
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/* Describe the devices in the Southbridge */
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/* Describe the devices in the Southbridge */
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#include "acpi/carrizo_fch.asl"
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#include <soc_fch.asl>
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} /* End \_SB scope */
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} /* End \_SB scope */
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@ -73,7 +73,7 @@ DefinitionBlock (
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#include <pci_int.asl>
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#include <pci_int.asl>
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/* Describe the devices in the Southbridge */
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/* Describe the devices in the Southbridge */
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#include "acpi/carrizo_fch.asl"
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#include <soc_fch.asl>
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} /* End \_SB scope */
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} /* End \_SB scope */
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