mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc

Code within carrizo_fch should be SOC specific instead of board specific.

BUG=b:64034810

Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22455
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel 2017-11-13 12:17:09 -07:00 committed by Aaron Durbin
parent bffff54e09
commit 519680948b
4 changed files with 2 additions and 121 deletions

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@ -1,119 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Device(AAHB) {
Name(_HID,"AAHB0000")
Name(_UID,0x0)
Name(_CRS, ResourceTemplate()
{
IRQ(Edge, ActiveHigh, Exclusive) {7}
Memory32Fixed(ReadWrite, 0xFEDC0000, 0x2000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(GPIO) {
Name (_HID, "AMD0030")
Name (_CID, "AMD0030")
Name(_UID, 0)
Name(_CRS, ResourceTemplate() {
Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(FUR0) {
Name(_HID,"AMD0020")
Name(_UID,0x0)
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {10}
Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(FUR1) {
Name(_HID,"AMD0020")
Name(_UID,0x1)
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {11}
Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(I2CA) {
Name(_HID,"AMD0010")
Name(_UID,0x0)
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {3}
Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(I2CB)
{
Name(_HID,"AMD0010")
Name(_UID,0x1)
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {15}
Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(I2CC) {
Name(_HID,"AMD0010")
Name(_UID,0x0)
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {6}
Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}
Device(I2CD)
{
Name(_HID,"AMD0010")
Name(_UID,0x1)
Name(_CRS, ResourceTemplate() {
IRQ(Edge, ActiveHigh, Exclusive) {14}
Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)
})
Method (_STA, 0x0, NotSerialized) {
Return (0x0F)
}
}

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@ -73,7 +73,7 @@ DefinitionBlock (
#include <pci_int.asl> #include <pci_int.asl>
/* Describe the devices in the Southbridge */ /* Describe the devices in the Southbridge */
#include "acpi/carrizo_fch.asl" #include <soc_fch.asl>
} /* End \_SB scope */ } /* End \_SB scope */

View File

@ -73,7 +73,7 @@ DefinitionBlock (
#include <pci_int.asl> #include <pci_int.asl>
/* Describe the devices in the Southbridge */ /* Describe the devices in the Southbridge */
#include "acpi/carrizo_fch.asl" #include <soc_fch.asl>
} /* End \_SB scope */ } /* End \_SB scope */