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mb/starlabs/labtop: Enable I2C4 

Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be
enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from
configuring anything regarding I2C4 (e.g. GPIOs).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Sean Rhodes 2021-12-20 21:35:05 +00:00 committed by Felix Held
parent 58f6a5d744
commit 51ab5e454d
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
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@ -28,6 +28,7 @@ chip soc/intel/tigerlake
# Serial I/O # Serial I/O
register "SerialIoI2cMode" = "{ register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
}" }"
register "SerialIoUartMode" = "{ register "SerialIoUartMode" = "{
@ -165,7 +166,7 @@ chip soc/intel/tigerlake
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[1]" = "1"
end end
device pci 19.0 off end # I2C4 device pci 19.0 on end # I2C4
device pci 19.1 off end # I2C5 device pci 19.1 off end # I2C5
device pci 19.2 on end # UART #2 device pci 19.2 on end # UART #2
device pci 1c.0 off end # PCI Express Port 1 device pci 1c.0 off end # PCI Express Port 1