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vboot: deprecate physical dev switch 

Currently only two devices make use of physical dev switch:
  stumpy, lumpy

Deprecate this switch.  If these devices are flashed to ToT,
they may still make use of virtual dev switch, activated
via recovery screen.

BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Joel Kitching 2019-03-17 18:07:25 +08:00 committed by Julius Werner
parent ed6996f2ba
commit 51bbdac7d5
11 changed files with 26 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/include/bootmode.h
View File

@ -19,7 +19,6 @@
/* functions implemented per mainboard: */
void init_bootmode_straps(void);
int get_write_protect_state(void);
int get_developer_mode_switch(void);
int get_recovery_mode_switch(void);
int get_recovery_mode_retrain_switch(void);
int clear_recovery_mode_switch(void);

1
src/mainboard/google/beltino/chromeos.c
View File

@ -26,7 +26,6 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>

1
src/mainboard/google/jecht/chromeos.c
View File

@ -27,7 +27,6 @@
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>

7
src/mainboard/intel/glkrvp/chromeos.c
View File

@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
@ -35,12 +34,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_developer_mode_switch(void)
{
/* No physical developer mode switch. It's virtual. */
return 0;
}
int get_write_protect_state(void)
{
return 0;

1
src/mainboard/samsung/lumpy/Kconfig
View File

@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
config VBOOT
select VBOOT_PHYSICAL_DEV_SWITCH
select VBOOT_PHYSICAL_REC_SWITCH
select VBOOT_VBNV_CMOS

46
src/mainboard/samsung/lumpy/chromeos.c
View File

@ -25,18 +25,16 @@
#define GPIO_SPI_WP 24
#define GPIO_REC_MODE 42
#define GPIO_DEV_MODE 17
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
#include "ec.h"
#include <ec/smsc/mec1308/ec.h>
#define GPIO_COUNT 6
#define GPIO_COUNT 5
void fill_lb_gpios(struct lb_gpios *gpios)
{
@ -60,28 +58,22 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->gpios[1].value = !get_recovery_mode_switch();
strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
/* Developer: GPIO17 = KBC3_DVP_MODE */
gpios->gpios[2].port = GPIO_DEV_MODE;
gpios->gpios[2].port = 100;
gpios->gpios[2].polarity = ACTIVE_HIGH;
gpios->gpios[2].value = get_developer_mode_switch();
strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
gpios->gpios[3].port = 100;
gpios->gpios[3].polarity = ACTIVE_HIGH;
gpios->gpios[3].value = lid & 1;
strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
gpios->gpios[2].value = lid & 1;
strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */
gpios->gpios[4].port = 101;
gpios->gpios[4].polarity = ACTIVE_LOW;
gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
gpios->gpios[3].port = 101;
gpios->gpios[3].polarity = ACTIVE_LOW;
gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1;
strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA Option ROM? */
gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[5].polarity = ACTIVE_HIGH;
gpios->gpios[5].value = gfx_get_init_done();
strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[4].polarity = ACTIVE_HIGH;
gpios->gpios[4].value = gfx_get_init_done();
strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH);
}
#endif
@ -95,16 +87,6 @@ int get_write_protect_state(void)
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_developer_mode_switch(void)
{
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
#else
struct device *dev = pcidev_on_root(0x1f, 2);
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
}
int get_recovery_mode_switch(void)
{
#ifdef __SIMPLE_DEVICE__
@ -130,16 +112,12 @@ void init_bootmode_straps(void)
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
if (get_gpio(GPIO_DEV_MODE))
flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};

1
src/mainboard/samsung/stumpy/Kconfig
View File

@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
config VBOOT
select VBOOT_PHYSICAL_DEV_SWITCH
select VBOOT_PHYSICAL_REC_SWITCH
select VBOOT_VBNV_CMOS

48
src/mainboard/samsung/stumpy/chromeos.c
View File

@ -24,16 +24,14 @@
#define GPIO_SPI_WP 68
#define GPIO_REC_MODE 42
#define GPIO_DEV_MODE 17
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
#define FLAG_DEV_MODE 2
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
#define GPIO_COUNT 6
#define GPIO_COUNT 5
void fill_lb_gpios(struct lb_gpios *gpios)
{
@ -56,29 +54,23 @@ void fill_lb_gpios(struct lb_gpios *gpios)
gpios->gpios[1].value = !get_recovery_mode_switch();
strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
/* Developer: GPIO17 = KBC3_DVP_MODE */
gpios->gpios[2].port = GPIO_DEV_MODE;
gpios->gpios[2].polarity = ACTIVE_HIGH;
gpios->gpios[2].value = get_developer_mode_switch();
strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
/* Hard code the lid switch GPIO to open. */
gpios->gpios[3].port = 100;
gpios->gpios[3].polarity = ACTIVE_HIGH;
gpios->gpios[3].value = 1;
strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
gpios->gpios[2].port = 100;
gpios->gpios[2].polarity = ACTIVE_HIGH;
gpios->gpios[2].value = 1;
strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */
gpios->gpios[4].port = 101;
gpios->gpios[4].polarity = ACTIVE_LOW;
gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
gpios->gpios[3].port = 101;
gpios->gpios[3].polarity = ACTIVE_LOW;
gpios->gpios[3].value = (gen_pmcon_1 >> 9) & 1;
strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA Option ROM? */
gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[5].polarity = ACTIVE_HIGH;
gpios->gpios[5].value = gfx_get_init_done();
strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
gpios->gpios[4].polarity = ACTIVE_HIGH;
gpios->gpios[4].value = gfx_get_init_done();
strncpy((char *)gpios->gpios[4].name,"oprom", GPIO_MAX_NAME_LENGTH);
}
#endif
@ -92,16 +84,6 @@ int get_write_protect_state(void)
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
}
int get_developer_mode_switch(void)
{
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
#else
struct device *dev = pcidev_on_root(0x1f, 2);
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
}
int get_recovery_mode_switch(void)
{
#ifdef __SIMPLE_DEVICE__
@ -127,16 +109,12 @@ void init_bootmode_straps(void)
/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
if (!get_gpio(GPIO_REC_MODE))
flags |= (1 << FLAG_REC_MODE);
/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
if (get_gpio(GPIO_DEV_MODE))
flags |= (1 << FLAG_DEV_MODE);
pci_write_config32(dev, SATA_SP, flags);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};

9
src/security/vboot/Kconfig
View File

@ -191,15 +191,6 @@ config VBOOT_SOFT_REBOOT_WORKAROUND
bool
default n
config VBOOT_PHYSICAL_DEV_SWITCH
bool
default n
help
Whether this platform has a physical developer switch. Note that this
disables virtual dev switch functionality (through secdata). Operation
where both a physical pin and the virtual switch get sampled is not
supported by coreboot.
config VBOOT_PHYSICAL_REC_SWITCH
bool
default n

3
src/security/vboot/vboot_handoff.c
View File

@ -79,8 +79,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff,
vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON;
}
/* TODO: Set these in depthcharge */
if (!CONFIG(VBOOT_PHYSICAL_DEV_SWITCH))
vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH;
vb_sd->flags |= VBSD_HONOR_VIRT_DEV_SWITCH;
if (!CONFIG(VBOOT_PHYSICAL_REC_SWITCH))
vb_sd->flags |= VBSD_BOOT_REC_SWITCH_VIRTUAL;
if (CONFIG(VBOOT_OPROM_MATTERS)) {

4
src/security/vboot/vboot_logic.c
View File

@ -324,10 +324,6 @@ void verstage_main(void)
die("Initializing measured boot mode failed!");
}
if (CONFIG(VBOOT_PHYSICAL_DEV_SWITCH) &&
get_developer_mode_switch())
ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;
if (get_recovery_mode_switch()) {
ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE;
if (CONFIG(VBOOT_DISABLE_DEV_ON_RECOVERY))