SMM: Fix state save map for sandybridge and TSEG
There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -117,8 +117,14 @@ void smi_handler(u32 smm_revision)
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{
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unsigned int node;
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smm_state_save_area_t state_save;
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u32 smm_base = 0xa8000; /* ASEG */
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#if !CONFIG_SMM_TSEG
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#if CONFIG_SMM_TSEG
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/* Update global variable TSEG base */
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if (!smi_get_tseg_base())
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return;
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smm_base = smi_get_tseg_base() + 0x8000;
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#else
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/* Are we ok to execute the handler? */
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if (!smi_obtain_lock()) {
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/* For security reasons we don't release the other CPUs
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@ -146,18 +152,22 @@ void smi_handler(u32 smm_revision)
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case 0x00030007:
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state_save.type = LEGACY;
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state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
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(0xa8000 + 0x7e00 - (node * 0x400));
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(smm_base + 0x7e00 - (node * 0x400));
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break;
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case 0x00030100:
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case 0x00030101: /* SandyBridge */
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state_save.type = EM64T;
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state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
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(0xa8000 + 0x7d00 - (node * 0x400));
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(smm_base + 0x7d00 - (node * 0x400));
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case 0x00030101: /* SandyBridge/IvyBridge */
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state_save.type = EM64T101;
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state_save.em64t101_state_save =
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(em64t101_smm_state_save_area_t *)
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(smm_base + 0x7d00 - (node * 0x400));
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break;
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case 0x00030064:
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state_save.type = AMD64;
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state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
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(0xa8000 + 0x7e00 - (node * 0x400));
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(smm_base + 0x7e00 - (node * 0x400));
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break;
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default:
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printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
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@ -201,6 +201,96 @@ typedef struct {
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} __attribute__((packed)) em64t_smm_state_save_area_t;
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/* Intel Revision 30101 SMM State-Save Area
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* Used in SandyBridge/IvyBridge architecture
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* starts @ 0x7d00
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*/
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typedef struct {
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u8 reserved0[208];
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u32 gdtr_upper_base;
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u32 ldtr_upper_base;
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u32 idtr_upper_base;
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u32 io_cf8;
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u64 io_rdi;
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u64 io_rip;
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u64 io_rcx;
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u64 io_rsi;
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u8 reserved1[52];
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u32 shutdown_auto_restart;
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u8 reserved2[8];
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u32 cr4;
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u8 reserved3[72];
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u32 gdtr_base;
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u8 reserved4[4];
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u32 idtr_base;
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u8 reserved5[4];
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u32 ldtr_base;
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u8 reserved6[68];
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u32 cs_base;
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u8 reserved7[4];
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u32 iedbase;
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u8 reserved8[8];
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u32 smbase;
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u32 smm_revision;
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u16 io_restart;
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u16 autohalt_restart;
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u8 reserved9[24];
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u64 r15;
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u64 r14;
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u64 r13;
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u64 r12;
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u64 r11;
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u64 r10;
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u64 r9;
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u64 r8;
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u64 rax;
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u64 rcx;
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u64 rdx;
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u64 rbx;
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u64 rsp;
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u64 rbp;
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u64 rsi;
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u64 rdi;
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u64 io_mem_addr;
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u32 io_misc_info;
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u32 es_sel;
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u32 cs_sel;
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u32 ss_sel;
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u32 ds_sel;
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u32 fs_sel;
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u32 gs_sel;
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u32 ldtr_sel;
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u32 tr_sel;
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u64 dr7;
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u64 dr6;
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u64 rip;
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u64 efer;
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u64 rflags;
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u64 cr3;
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u64 cr0;
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} __attribute__((packed)) em64t101_smm_state_save_area_t;
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/* Legacy x86 SMM State-Save Area
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* starts @ 0x7e00
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*/
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@ -243,6 +333,7 @@ typedef struct {
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typedef enum {
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AMD64,
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EM64T,
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EM64T101,
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LEGACY
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} save_state_type_t;
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@ -252,6 +343,7 @@ typedef struct {
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union {
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amd64_smm_state_save_area_t *amd64_state_save;
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em64t_smm_state_save_area_t *em64t_state_save;
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em64t101_smm_state_save_area_t *em64t101_state_save;
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legacy_smm_state_save_area_t *legacy_state_save;
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};
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} smm_state_save_area_t;
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@ -284,6 +376,9 @@ void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ);
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#if !CONFIG_SMM_TSEG
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void smi_release_lock(void);
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#else
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/* Return address of TSEG base */
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u32 smi_get_tseg_base(void);
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#endif
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#endif
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@ -32,6 +32,13 @@
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#include "nvs.h"
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/* We are using PCIe accesses for now
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* 1. the chipset can do it
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* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
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*/
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/pcie_config.c>
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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@ -47,6 +54,12 @@ void *smi1 = (void *)0x0;
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#if CONFIG_SMM_TSEG
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static u32 tseg_base = 0;
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u32 smi_get_tseg_base(void)
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{
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if (!tseg_base)
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tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
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return tseg_base;
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}
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static inline void tseg_fixup(void **ptr)
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{
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/* Adjust pointer with TSEG base */
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@ -208,13 +221,6 @@ static void dump_tco_status(u32 tco_sts)
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printk(BIOS_DEBUG, "\n");
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}
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/* We are using PCIe accesses for now
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* 1. the chipset can do it
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* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
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*/
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/pcie_config.c>
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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@ -672,11 +678,6 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
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/* Update global variable pmbase */
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pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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#if CONFIG_SMM_TSEG
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/* Update global variable TSEG base */
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tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
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#endif
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/* We need to clear the SMI status registers, or we won't see what's
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* happening in the following calls.
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*/
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@ -688,7 +689,8 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
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if (southbridge_smi[i]) {
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#if CONFIG_SMM_TSEG
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smi_handler_t handler = (smi_handler_t)
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((u8*)southbridge_smi[i] + tseg_base);
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((u8*)southbridge_smi[i] +
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smi_get_tseg_base());
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if (handler)
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handler(node, state_save);
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#else
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