cpu/amd/fam10h-fam15h: Bring HT register configuration in line with BKDG
The existing HyperTransport register configuration values were incorrect in many spots. Apply the correct values from the BKDG on Family 10h and Family 15h processors. Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12022 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson
Stefan Reinauer
parent
371d291df5
commit
51cfbcddde
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@ -371,44 +371,140 @@ static const struct {
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[2] SyncOnUcEccEn = 1 */
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/* XBAR buffer settings */
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{ 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00018052, 0x700780f7 },
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{ 3, 0x6c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
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0x00018052, 0x700780f7 }, /* IsocRspDBC = 0x0,
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UpRspDBC = 0x1,
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DatBuf24 = 0x1,
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DnRspDBC = 0x1,
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DnReqDBC = 0x1,
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UpReqDBC = 0x2 */
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/* XBAR buffer settings */
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{ 3, 0x6c, AMD_DR_Dx, AMD_PTYPE_ALL,
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0x00028052, 0x700780f7 }, /* IsocRspDBC = 0x0,
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UpRspDBC = 0x2,
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DatBuf24 = 0x1,
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DnRspDBC = 0x1,
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DnReqDBC = 0x1,
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UpReqDBC = 0x2 */
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/* XBAR buffer settings */
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{ 3, 0x6c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
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0x10010052, 0x700700f7 },
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0x10010052, 0x700700f7 }, /* IsocRspDBC = 0x1,
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UpRspDBC = 0x1,
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DnRspDBC = 0x1,
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DnReqDBC = 0x1,
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UpReqDBC = 0x2 */
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/* Errata 281 Workaround */
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{ 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1),
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{ 3, 0x6c, (AMD_DR_B0 | AMD_DR_B1),
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AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
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{ 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
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{ 3, 0x6c, AMD_FAM10_ALL, AMD_PTYPE_UMA,
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0x60018051, 0x700780F7 },
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{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00041153, 0x777777F7 },
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{ 3, 0x70, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
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0x00041153, 0x777777f7 }, /* IsocRspCBC = 0x0,
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IsocPreqCBC = 0x0,
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IsocReqCBC = 0x0,
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UpRspCBC = 0x4,
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DnPreqCBC = 0x1,
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UpPreqCBC = 0x1,
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DnRspCBC = 0x1,
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DnReqCBC = 0x1,
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UpReqCBC = 0x3 */
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{ 3, 0x70, AMD_DR_Dx, AMD_PTYPE_ALL,
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0x00051153, 0x777777f7 }, /* IsocRspCBC = 0x0,
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IsocPreqCBC = 0x0,
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IsocReqCBC = 0x0,
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UpRspCBC = 0x5,
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DnPreqCBC = 0x1,
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UpPreqCBC = 0x1,
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DnRspCBC = 0x1,
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DnReqCBC = 0x1,
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UpReqCBC = 0x3 */
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{ 3, 0x70, AMD_FAM15_ALL, AMD_PTYPE_ALL,
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0x10171155, 0x777777f7 },
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0x10171155, 0x777777f7 }, /* IsocRspCBC = 0x1,
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IsocPreqCBC = 0x0,
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IsocReqCBC = 0x1,
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UpRspCBC = 0x7,
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DnPreqCBC = 0x1,
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UpPreqCBC = 0x1,
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DnRspCBC = 0x1,
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DnReqCBC = 0x1,
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UpReqCBC = 0x5 */
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{ 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
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0x61221151, 0x777777F7 },
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0x61221151, 0x777777f7 }, /* IsocRspCBC = 0x6,
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IsocPreqCBC = 0x1,
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IsocReqCBC = 0x2,
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UpRspCBC = 0x2,
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DnPreqCBC = 0x1,
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UpPreqCBC = 0x1,
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DnRspCBC = 0x1,
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DnReqCBC = 0x1,
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UpReqCBC = 0x1 */
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{ 3, 0x74, AMD_FAM10_ALL, ~AMD_PTYPE_UMA,
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0x00081111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
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IsocPreqCBC = 0x0,
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IsocReqCBC = 0x0,
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ProbeCBC = 0x8,
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DnPreqCBC = 0x1,
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UpPreqCBC = 0x1,
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DnReqCBC = 0x1,
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UpReqCBC = 0x1 */
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{ 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
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0x00080101, 0x000F7777 },
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0x00480101, 0xf7ff7777 }, /* DRReqCBC = 0x0,
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IsocPreqCBC = 0x0,
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IsocReqCBC = 0x4,
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ProbeCBC = 0x8,
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DnPreqCBC = 0x0,
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UpPreqCBC = 0x1,
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DnReqCBC = 0x0,
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UpReqCBC = 0x1 */
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{ 3, 0x74, AMD_FAM15_ALL, AMD_PTYPE_ALL,
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0x00172111, 0x77ff7777 },
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0x00172111, 0xf7ff7777 }, /* DRReqCBC = 0x0,
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IsocPreqCBC = 0x0,
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IsocReqCBC = 0x1,
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ProbeCBC = 0x7,
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DnPreqCBC = 0x2,
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UpPreqCBC = 0x1,
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DnReqCBC = 0x1,
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UpReqCBC = 0x1 */
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{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
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0x00090914, 0x707FFF1F },
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{ 3, 0x7c, AMD_FAM10_ALL & ~(AMD_DR_Dx), AMD_PTYPE_ALL,
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0x00090914, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
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Sri2XbarFreeRspDBC = 0x0,
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Sri2XbarFreeXreqDBC = 0x9,
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Sri2XbarFreeRspCBC = 0x0,
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Sri2XbarFreeXreqCBC = 0x9,
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Xbar2SriFreeListCBC = 0x14 */
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{ 3, 0x7c, AMD_DR_Dx, AMD_PTYPE_ALL,
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0x00090a18, 0x707fff1f }, /* XBar2SriFreeListCBInc = 0x0,
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Sri2XbarFreeRspDBC = 0x0,
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Sri2XbarFreeXreqDBC = 0x9,
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Sri2XbarFreeRspCBC = 0x0,
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Sri2XbarFreeXreqCBC = 0x9,
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Xbar2SriFreeListCBC = 0x14 */
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/* Errata 281 Workaround */
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{ 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
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AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
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{ 3, 0x7C, AMD_FAM15_ALL, AMD_PTYPE_ALL,
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0x040d0f16, 0x07ffff1f },
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{ 3, 0x7c, AMD_FAM15_ALL, AMD_PTYPE_ALL,
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0x040d0f16, 0x77ffff1f }, /* XBar2SriFreeListCBInc = 0x0,
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SrqExtFreeListBC = 0x8,
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Sri2XbarFreeRspDBC = 0x0,
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Sri2XbarFreeXreqDBC = 0xd,
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Sri2XbarFreeRspCBC = 0x0,
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Sri2XbarFreeXreqCBC = 0xf,
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Xbar2SriFreeListCBC = 0x16 */
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{ 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
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0x00070814, 0x007FFF1F },
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@ -630,18 +726,16 @@ static const struct {
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0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
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{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
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0x00000000, 0x000000FF }, /* Provide clear setting for logical
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completeness */
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0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
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{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
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0x00000000, 0x000000FF }, /* Provide clear setting for logical
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completeness */
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0x0000005a, 0x000000ff }, /* Use common "safe" setting for K10 */
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{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
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0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
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0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
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{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
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0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
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0x0000006d, 0x000000ff }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
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/* Link Phy Receiver Loop Filter Registers */
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{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
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@ -664,24 +758,29 @@ static const struct {
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0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
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[20:16] RttIndex = 04h */
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/* FIXME
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* Causes lockups for some reason when more than one package is installed
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* Debug and reactivate!
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*/
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// #if 0
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{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
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0x00000000, 0x000000FF }, /* Provide clear setting for logical
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completeness */
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0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
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P0XmtRdPtr = 0x2
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P1RcvRdPtr = 0xa
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P1XmtRdPtr = 0x0 */
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{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
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0x00000000, 0x000000FF }, /* Provide clear setting for logical
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completeness */
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0x00000a2a, 0x000000ff }, /* P0RcvRdPtr = 0xa,
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P0XmtRdPtr = 0x2
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P1RcvRdPtr = 0xa
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P1XmtRdPtr = 0x0 */
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{ 0xCF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
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0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
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0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
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P0XmtRdPtr = 0x4
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P1RcvRdPtr = 0xd
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P1XmtRdPtr = 0x0 */
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{ 0xDF, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
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0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
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0x00000d4d, 0x000000ff }, /* P0RcvRdPtr = 0xd,
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P0XmtRdPtr = 0x4
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P1RcvRdPtr = 0xd
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P1XmtRdPtr = 0x0 */
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/* Link Phy Receiver Loop Filter Registers */
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{ 0xD1, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
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@ -703,5 +802,4 @@ static const struct {
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{ 0xC0, AMD_FAM15_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
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0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
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[20:16] RttIndex = 04h */
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// #endif
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};
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