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soc/intel/apollolake: Add lpss dsdt entry 

Add southbridge and LPSS device DSDT table.

Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14218
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Zhao, Lijian 2016-01-20 13:02:38 -08:00 committed by Martin Roth
parent 30461a9197
commit 51d43fc9c5
2 changed files with 125 additions and 0 deletions
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111
src/soc/intel/apollolake/acpi/lpss.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
scope (\_SB.PCI0) {
/* LPIO1 PWM */
Device(PWM) {
Name (_ADR, 0x001A0000)
Name (_DDN, "Intel(R) PWM Controller")
}
/* LPIO1 HS-UART #1 */
Device(URT1) {
Name (_ADR, 0x00180000)
Name (_DDN, "Intel(R) HS-UART Controller #1")
}
/* LPIO1 HS-UART #2 */
Device(URT2) {
Name (_ADR, 0x00180001)
Name (_DDN, "Intel(R) HS-UART Controller #2")
}
/* LPIO1 HS-UART #3 */
Device(URT3) {
Name (_ADR, 0x00180002)
Name (_DDN, "Intel(R) HS-UART Controller #3")
}
/* LPIO1 HS-UART #4 */
Device(URT4) {
Name (_ADR, 0x00180003)
Name (_DDN, "Intel(R) HS-UART Controller #4")
}
/* LPIO1 SPI */
Device(SPI1) {
Name (_ADR, 0x00190000)
Name (_DDN, "Intel(R) SPI Controller #1")
}
/* LPIO1 SPI #2 */
Device(SPI2) {
Name (_ADR, 0x00190001)
Name (_DDN, "Intel(R) SPI Controller #2")
}
/* LPIO1 SPI #3 */
Device(SPI3) {
Name (_ADR, 0x00190002)
Name (_DDN, "Intel(R) SPI Controller #3")
}
/* LPIO2 I2C #0 */
Device(I2C0) {
Name (_ADR, 0x00160000)
Name (_DDN, "Intel(R) I2C Controller #0")
}
/* LPIO2 I2C #1 */
Device(I2C1) {
Name (_ADR, 0x00160001)
Name (_DDN, "Intel(R) I2C Controller #1")
}
/* LPIO2 I2C #2 */
Device(I2C2) {
Name (_ADR, 0x00160002)
Name (_DDN, "Intel(R) I2C Controller #2")
}
/* LPIO2 I2C #3 */
Device(I2C3) {
Name (_ADR, 0x00160003)
Name (_DDN, "Intel(R) I2C Controller #3")
}
/* LPIO2 I2C #4 */
Device(I2C4) {
Name (_ADR, 0x00170000)
Name (_DDN, "Intel(R) I2C Controller #4")
}
/* LPIO2 I2C #5 */
Device(I2C5) {
Name (_ADR, 0x00170001)
Name (_DDN, "Intel(R) I2C Controller #5")
}
/* LPIO2 I2C #6 */
Device(I2C6) {
Name (_ADR, 0x00170002)
Name (_DDN, "Intel(R) I2C Controller #6")
}
/* LPIO2 I2C #7 */
Device(I2C7) {
Name (_ADR, 0x00170003)
Name (_DDN, "Intel(R) I2C Controller #7")
}
}

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src/soc/intel/apollolake/acpi/southbridge.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/* LPSS device */
#include "lpss.asl"