mb/google/nissa: Add gpio lock pins
Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai
Felix Held
parent
4d4a24529a
commit
51e00e60e0
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@ -29,13 +29,13 @@ static const struct pad_config gpio_table[] = {
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/* A12 : NC */
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PAD_NC(GPP_A12, NONE),
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* A14 : USB_OC1# ==> NC */
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PAD_NC(GPP_A14, NONE),
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/* A15 : USB_OC2# ==> NC */
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PAD_NC(GPP_A15, NONE),
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/* A16 : USB_OC3# ==> NC */
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PAD_NC(GPP_A16, NONE),
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PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
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/* A17 : NC */
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PAD_NC(GPP_A17, NONE),
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/* A18 : NC */
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@ -58,17 +58,17 @@ static const struct pad_config gpio_table[] = {
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/* B2 : NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : NC */
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PAD_NC(GPP_B3, NONE),
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PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
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/* B4 : NC */
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PAD_NC(GPP_B4, NONE),
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PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
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/* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
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/* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
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/* B7 : I2C3_SDA ==> SOC_I2C_AUDIO_SDA */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
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PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
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/* B8 : I2C3_SCL ==> SOC_I2C_AUDIO_SCL */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
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PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
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/* B9 : Not available */
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PAD_NC(GPP_B9, NONE),
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/* B10 : Not available */
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@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = {
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/* B13 : PLTRST# ==> PLT_RST_L */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* B14 : SPKR ==> GPP_B14_STRAP */
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PAD_NC(GPP_B14, NONE),
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PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
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/* B15 : NC */
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PAD_NC(GPP_B15, NONE),
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PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
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/* B16 : I2C5_SDA ==> SOC_I2C_TCHPAD_SDA */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
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PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
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/* B17 : I2C5_SCL ==> SOC_I2C_TCHPAD_SCL */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
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PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
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/* B18 : GPP_B18 ==> GPP_B18_STRAP */
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PAD_NC(GPP_B18, NONE),
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/* B19 : Not available */
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@ -118,13 +118,13 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
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/* D0 : NC */
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PAD_NC(GPP_D0, NONE),
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PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
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/* D1 : NC */
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PAD_NC(GPP_D1, NONE),
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PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
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/* D2 : NC */
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PAD_NC(GPP_D2, NONE),
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PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
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/* D3 : ISH_GP3 ==> WCAM_RST_L */
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PAD_CFG_GPO(GPP_D3, 0, DEEP),
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PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
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/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* D5 : NC */
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@ -136,34 +136,34 @@ static const struct pad_config gpio_table[] = {
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/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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/* D9 : NC */
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PAD_NC(GPP_D9, NONE),
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PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
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/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
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PAD_NC(GPP_D10, NONE),
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PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
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/* D11 : NC */
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PAD_NC(GPP_D11, NONE),
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PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
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/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
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PAD_NC(GPP_D12, NONE),
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PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
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/* D13 : NC */
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PAD_NC(GPP_D13, NONE),
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PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
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/* D14 : NC */
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PAD_NC(GPP_D14, NONE),
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PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
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/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
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/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
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PAD_CFG_GPO(GPP_D16, 0, DEEP),
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PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
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/* D17 : NC */
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PAD_NC(GPP_D17, NONE),
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PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
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/* D18 : NC */
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PAD_NC(GPP_D18, NONE),
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PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
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/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* E0 : NC */
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PAD_NC(GPP_E0, NONE),
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/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E1, NONE, DEEP),
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PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
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/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
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/* E3 : PROC_GP0 ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E3, NONE, DEEP),
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/* E4 : NC */
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@ -171,21 +171,21 @@ static const struct pad_config gpio_table[] = {
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/* E5 : NC */
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PAD_NC(GPP_E5, NONE),
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/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
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PAD_NC(GPP_E6, NONE),
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PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
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/* E7 : NC */
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PAD_NC(GPP_E7, NONE),
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/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
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PAD_CFG_GPO(GPP_E8, 1, DEEP),
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/* E9 : NC */
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PAD_NC(GPP_E9, NONE),
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PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
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/* E10 : NC */
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PAD_NC(GPP_E10, NONE),
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PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
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/* E11 : NC */
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PAD_NC(GPP_E11, NONE),
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PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
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PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
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/* E13 : NC */
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PAD_NC(GPP_E13, NONE),
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PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
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/* E14 : DDSP_HPDA ==> EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : NC */
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@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
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/* E16 : NC */
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PAD_NC(GPP_E16, NONE),
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/* E17 : NC */
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PAD_NC(GPP_E17, NONE),
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PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
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/* E18 : NC */
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PAD_NC(GPP_E18, NONE),
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/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
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@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = {
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/* F10 : GPP_F10 ==> GPP_F10_STRAP */
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PAD_NC(GPP_F10, NONE),
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/* F11 : NC */
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PAD_NC(GPP_F11, NONE),
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PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
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/* F12 : GSXDOUT ==> WWAN_RST_L */
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PAD_CFG_GPO(GPP_F12, 1, DEEP),
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PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
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/* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP),
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PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_F13, NONE, LOCK_CONFIG),
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/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT),
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PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, DEEP, EDGE_SINGLE),
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PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG),
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/* F16 : NC */
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PAD_NC(GPP_F16, NONE),
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PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
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/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
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PAD_CFG_GPI_SCI(GPP_F17, NONE, DEEP, LEVEL, INVERT),
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PAD_CFG_GPI_SCI_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
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/* F19 : Not available */
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PAD_NC(GPP_F19, NONE),
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/* F20 : Not available */
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@ -263,11 +263,11 @@ static const struct pad_config gpio_table[] = {
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/* H2 : GPP_H2_STRAP */
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PAD_NC(GPP_H2, NONE),
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/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
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PAD_CFG_GPI_SCI_LOW(GPP_H3, NONE, DEEP, EDGE_SINGLE),
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PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
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/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
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/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
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/* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
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@ -281,9 +281,9 @@ static const struct pad_config gpio_table[] = {
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H12 : UART0_RTS# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H12, 1, DEEP),
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PAD_CFG_GPO_LOCK(GPP_H12, 1, LOCK_CONFIG),
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/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
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PAD_CFG_GPO(GPP_H13, 1, DEEP),
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PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
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/* H14 : Not available */
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PAD_NC(GPP_H14, NONE),
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/* H15 : NC */
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