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soc/intel/alderlake: Enable LPIT support 

Add SLP_S0 residency register and enable LPIT support.

Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jeremy Soller 2022-05-26 09:02:13 -06:00 committed by Paul Fagerburg
parent dca8583f17
commit 5219ee160e
2 changed files with 3 additions and 0 deletions
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1
src/soc/intel/alderlake/Kconfig
View File

@ -83,6 +83,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ
select SOC_INTEL_COMMON_BLOCK_CAR

2
src/soc/intel/alderlake/include/soc/pmc.h
View File

@ -153,6 +153,8 @@ extern struct device_operations pmc_ops;
#define HPR_CAUSE0_MI_HRPC (1 << 9)
#define HPR_CAUSE0_MI_HR (1 << 8)
#define SLP_S0_RES 0x193c
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)