soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
praveen hodagatta pranesh
Patrick Georgi
parent
e26c4a4611
commit
521e48c87d
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@ -10,7 +10,7 @@ config SOC_INTEL_COFFEELAKE
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help
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Intel Coffeelake support
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config CANNONLAKE_SOC_PCH_H
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config SOC_INTEL_CANNONLAKE_PCH_H
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bool
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default n
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help
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@ -165,7 +165,7 @@ config NHLT_DA7219
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config MAX_ROOT_PORTS
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int
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default 24 if CANNONLAKE_SOC_PCH_H
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default 24 if SOC_INTEL_CANNONLAKE_PCH_H
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default 16
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config SMM_TSEG_SIZE
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@ -204,7 +204,7 @@ config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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config SOC_INTEL_I2C_DEV_MAX
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int
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default 4 if CANNONLAKE_SOC_PCH_H
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default 4 if SOC_INTEL_CANNONLAKE_PCH_H
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default 6
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# Clock divider parameters for 115200 baud rate
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@ -13,7 +13,6 @@ bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += pmutil.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += memmap.c
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@ -23,7 +22,6 @@ bootblock-y += p2sb.c
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bootblock-$(CONFIG_UART_DEBUG) += uart.c
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romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_MEMCFG_INIT) += cnl_memcfg_init.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += lpc.c
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@ -38,10 +36,8 @@ ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += gspi.c
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ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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@ -58,7 +54,6 @@ ramstage-$(CONFIG_UART_DEBUG) += uart.c
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ramstage-y += vr_config.c
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ramstage-y += sd.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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@ -77,6 +72,18 @@ verstage-y += pmutil.c
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verstage-y += spi.c
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verstage-$(CONFIG_UART_DEBUG) += uart.c
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ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
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bootblock-y += gpio_cnp_h.c
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romstage-y += gpio_cnp_h.c
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ramstage-y += gpio_cnp_h.c
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smm-y += gpio_cnp_h.c
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else
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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smm-y += gpio.c
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
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@ -0,0 +1,128 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <soc/gpio_defs_cnp_h.h>
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#include <soc/irq.h>
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#include <soc/pcr_ids.h>
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Device (GPIO)
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{
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Name (_HID, "INT3450")
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Name (_UID, 0)
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Name (_DDN, "GPIO Controller")
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Name (RBUF, ResourceTemplate()
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{
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Memory32Fixed (ReadWrite, 0, 0, COM0)
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Memory32Fixed (ReadWrite, 0, 0, COM1)
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Memory32Fixed (ReadWrite, 0, 0, COM2)
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Memory32Fixed (ReadWrite, 0, 0, COM3)
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Memory32Fixed (ReadWrite, 0, 0, COM4)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
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{ GPIO_IRQ14 }
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})
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Method (_CRS, 0, NotSerialized)
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{
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/* GPIO Community 0 */
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CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
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CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
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Store (^^PCRB (PID_GPIOCOM0), BAS0)
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Store (GPIO_BASE_SIZE, LEN0)
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/* GPIO Community 1 */
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CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
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CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
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Store (^^PCRB (PID_GPIOCOM1), BAS1)
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Store (GPIO_BASE_SIZE, LEN1)
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/* GPIO Community 2 */
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CreateDWordField (^RBUF, ^COM2._BAS, BAS2)
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CreateDWordField (^RBUF, ^COM2._LEN, LEN2)
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Store (^^PCRB (PID_GPIOCOM2), BAS2)
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Store (GPIO_BASE_SIZE, LEN2)
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/* GPIO Community 3 */
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CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
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CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
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Store (^^PCRB (PID_GPIOCOM3), BAS3)
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Store (GPIO_BASE_SIZE, LEN3)
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/* GPIO Community 4 */
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CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
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CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
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Store (^^PCRB (PID_GPIOCOM4), BAS4)
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Store (GPIO_BASE_SIZE, LEN4)
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Return (RBUF)
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}
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Method (_STA, 0, NotSerialized)
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{
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Return (0xF)
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}
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}
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/*
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* Get GPIO DW0 Address
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* Arg0 - GPIO Number
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*/
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Method (GADD, 1, NotSerialized)
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{
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/* GPIO Community 0 */
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If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
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{
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Store (PID_GPIOCOM0, Local0)
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Subtract (Arg0, GPP_A0, Local1)
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}
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/* GPIO Community 1 */
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If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7)))
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{
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Store (PID_GPIOCOM1, Local0)
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Subtract (Arg0, GPP_C0, Local1)
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}
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/* GPIO Community 3*/
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If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23)))
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{
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Store (PID_GPIOCOM3, Local0)
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Subtract (Arg0, GPP_K0, Local1)
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}
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/* GPIO Community 4*/
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If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11)))
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{
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Store (PID_GPIOCOM4, Local0)
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Subtract (Arg0, GPP_I0, Local1)
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}
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Store (PCRB (Local0), Local2)
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Add (Local2, PAD_CFG_BASE, Local2)
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Return (Add (Local2, Multiply (Local1, 16)))
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}
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/*
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* Get GPIO Value
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* Arg0 - GPIO Number
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*/
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Method (GRXS, 1, Serialized)
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{
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OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
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Field (PREG, AnyAcc, NoLock, Preserve)
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{
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VAL0, 32
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}
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And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
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Return (Local0)
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}
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@ -33,7 +33,11 @@
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#include "scs.asl"
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/* GPIO controller */
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#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
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#include "gpio_cnp_h.asl"
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#else
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#include "gpio.asl"
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#endif
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/* LPC 0:1f.0 */
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#include "lpc.asl"
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@ -24,12 +24,18 @@
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#include <stdint.h>
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#include <soc/gpio.h>
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#include <soc/pch.h>
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#include <soc/gpio_defs.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
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#include <soc/gpio_defs_cnp_h.h>
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#else
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#include <soc/gpio_defs.h>
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#endif
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struct soc_intel_cannonlake_config {
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@ -0,0 +1,170 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/gpio.h>
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#include <intelblocks/pcr.h>
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#include <soc/pcr_ids.h>
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#include <soc/pmc.h>
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static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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};
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static const struct reset_mapping rst_map_com0[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
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};
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static const struct pad_group cnl_community0_groups[] = {
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INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP_A */
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INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP_B */
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};
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static const struct pad_group cnl_community1_groups[] = {
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INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
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INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP_D */
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INTEL_GPP(GPP_C0, GPP_G0, GPP_G7), /* GPP_G */
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};
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static const struct pad_group cnl_community2_groups[] = {
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INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */
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};
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static const struct pad_group cnl_community3_groups[] = {
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INTEL_GPP(GPP_K0, GPP_K0, GPP_K23), /* GPP_K*/
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INTEL_GPP(GPP_K0, GPP_H0, GPP_H23), /* GPP_H */
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INTEL_GPP(GPP_K0, GPP_E0, GPP_E12), /* GPP_E */
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INTEL_GPP(GPP_K0, GPP_F0, GPP_F23), /* GPP_F */
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};
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static const struct pad_group cnl_community4_groups[] = {
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INTEL_GPP(GPP_I0, GPP_I0, GPP_I14), /* GPP_I */
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INTEL_GPP(GPP_I0, GPP_J0, GPP_J11), /* GPP_J */
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};
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static const struct pad_community cnl_communities[] = {
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{ /* GPP A, B */
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.port = PID_GPIOCOM0,
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.first_pad = GPP_A0,
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.last_pad = GPP_B23,
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.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_AB",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map_com0,
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.num_reset_vals = ARRAY_SIZE(rst_map_com0),
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.groups = cnl_community0_groups,
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.num_groups = ARRAY_SIZE(cnl_community0_groups),
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}, { /* GPP C, D, G */
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.port = PID_GPIOCOM1,
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.first_pad = GPP_C0,
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.last_pad = GPP_G7,
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.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_CDG",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = cnl_community1_groups,
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.num_groups = ARRAY_SIZE(cnl_community1_groups),
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}, { /* GPD */
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.port = PID_GPIOCOM2,
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.first_pad = GPD0,
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.last_pad = GPD11,
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.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPD",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = cnl_community2_groups,
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.num_groups = ARRAY_SIZE(cnl_community2_groups),
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}, { /* GPP K, H, E, F */
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.port = PID_GPIOCOM3,
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.first_pad = GPP_K0,
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.last_pad = GPP_F23,
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.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_KHEF",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = cnl_community3_groups,
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.num_groups = ARRAY_SIZE(cnl_community3_groups),
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}, { /* GPP I, J */
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.port = PID_GPIOCOM4,
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.first_pad = GPP_I0,
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.last_pad = GPP_J11,
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.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPP_IJ",
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.acpi_path = "\\_SB.PCI0.GPIO",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = cnl_community4_groups,
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.num_groups = ARRAY_SIZE(cnl_community4_groups),
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}
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};
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const struct pad_community *soc_gpio_get_community(size_t *num_communities)
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{
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*num_communities = ARRAY_SIZE(cnl_communities);
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return cnl_communities;
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}
|
||||
|
||||
const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
|
||||
{
|
||||
static const struct pmc_to_gpio_route routes[] = {
|
||||
{ PMC_GPP_A, GPP_A },
|
||||
{ PMC_GPP_B, GPP_B },
|
||||
{ PMC_GPP_C, GPP_C },
|
||||
{ PMC_GPP_D, GPP_D },
|
||||
{ PMC_GPP_E, GPP_E },
|
||||
{ PMC_GPP_F, GPP_F },
|
||||
{ PMC_GPP_G, GPP_G },
|
||||
{ PMC_GPP_H, GPP_H },
|
||||
{ PMC_GPP_I, GPP_I },
|
||||
{ PMC_GPP_J, GPP_J },
|
||||
{ PMC_GPP_K, GPP_K },
|
||||
{ PMC_GPD, GPD },
|
||||
};
|
||||
*num = ARRAY_SIZE(routes);
|
||||
return routes;
|
||||
}
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Intel Corporation.
|
||||
* Copyright (C) 2017-2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -16,9 +16,14 @@
|
|||
#ifndef _SOC_CANNONLAKE_GPIO_H_
|
||||
#define _SOC_CANNONLAKE_GPIO_H_
|
||||
|
||||
|
||||
#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
|
||||
#include <soc/gpio_defs_cnp_h.h>
|
||||
#define CROS_GPIO_DEVICE_NAME "INT3450:00"
|
||||
#else
|
||||
#include <soc/gpio_defs.h>
|
||||
#define CROS_GPIO_DEVICE_NAME "INT34BB:00"
|
||||
#endif
|
||||
#include <intelblocks/gpio.h>
|
||||
|
||||
#define CROS_GPIO_DEVICE_NAME "INT34BB:00"
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,329 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_
|
||||
#define _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_
|
||||
|
||||
#ifndef __ACPI__
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
#include <soc/gpio_soc_defs_cnp_h.h>
|
||||
|
||||
|
||||
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
|
||||
|
||||
#define NUM_GPIO_COMx_GPI_REGS(n) \
|
||||
(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
|
||||
|
||||
#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
|
||||
#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
|
||||
#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS)
|
||||
#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
|
||||
#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
|
||||
|
||||
#define NUM_GPI_STATUS_REGS \
|
||||
((NUM_GPIO_COM0_GPI_REGS) +\
|
||||
(NUM_GPIO_COM1_GPI_REGS) +\
|
||||
(NUM_GPIO_COM2_GPI_REGS) +\
|
||||
(NUM_GPIO_COM3_GPI_REGS) +\
|
||||
(NUM_GPIO_COM4_GPI_REGS))
|
||||
/*
|
||||
* IOxAPIC IRQs for the GPIOs
|
||||
*/
|
||||
|
||||
/* Group A */
|
||||
#define GPP_A0_IRQ 0x18
|
||||
#define GPP_A1_IRQ 0x19
|
||||
#define GPP_A2_IRQ 0x1a
|
||||
#define GPP_A3_IRQ 0x1b
|
||||
#define GPP_A4_IRQ 0x1c
|
||||
#define GPP_A5_IRQ 0x1d
|
||||
#define GPP_A6_IRQ 0x1e
|
||||
#define GPP_A7_IRQ 0x1f
|
||||
#define GPP_A8_IRQ 0x20
|
||||
#define GPP_A9_IRQ 0x21
|
||||
#define GPP_A10_IRQ 0x22
|
||||
#define GPP_A11_IRQ 0x23
|
||||
#define GPP_A12_IRQ 0x24
|
||||
#define GPP_A13_IRQ 0x25
|
||||
#define GPP_A14_IRQ 0x26
|
||||
#define GPP_A15_IRQ 0x27
|
||||
#define GPP_A16_IRQ 0x28
|
||||
#define GPP_A17_IRQ 0x29
|
||||
#define GPP_A18_IRQ 0x2a
|
||||
#define GPP_A19_IRQ 0x2b
|
||||
#define GPP_A20_IRQ 0x2c
|
||||
#define GPP_A21_IRQ 0x2d
|
||||
#define GPP_A22_IRQ 0x2e
|
||||
#define GPP_A23_IRQ 0x2f
|
||||
/* Group B */
|
||||
#define GPP_B0_IRQ 0x30
|
||||
#define GPP_B1_IRQ 0x31
|
||||
#define GPP_B2_IRQ 0x32
|
||||
#define GPP_B3_IRQ 0x33
|
||||
#define GPP_B4_IRQ 0x34
|
||||
#define GPP_B5_IRQ 0x35
|
||||
#define GPP_B6_IRQ 0x36
|
||||
#define GPP_B7_IRQ 0x37
|
||||
#define GPP_B8_IRQ 0x38
|
||||
#define GPP_B9_IRQ 0x39
|
||||
#define GPP_B10_IRQ 0x3a
|
||||
#define GPP_B11_IRQ 0x3b
|
||||
#define GPP_B12_IRQ 0x3c
|
||||
#define GPP_B13_IRQ 0x3d
|
||||
#define GPP_B14_IRQ 0x3e
|
||||
#define GPP_B15_IRQ 0x3f
|
||||
#define GPP_B16_IRQ 0x40
|
||||
#define GPP_B17_IRQ 0x41
|
||||
#define GPP_B18_IRQ 0x42
|
||||
#define GPP_B19_IRQ 0x43
|
||||
#define GPP_B20_IRQ 0x44
|
||||
#define GPP_B21_IRQ 0x45
|
||||
#define GPP_B22_IRQ 0x46
|
||||
#define GPP_B23_IRQ 0x47
|
||||
/* Group C */
|
||||
#define GPP_C0_IRQ 0x48
|
||||
#define GPP_C1_IRQ 0x49
|
||||
#define GPP_C2_IRQ 0x4a
|
||||
#define GPP_C3_IRQ 0x4b
|
||||
#define GPP_C4_IRQ 0x4c
|
||||
#define GPP_C5_IRQ 0x4d
|
||||
#define GPP_C6_IRQ 0x4e
|
||||
#define GPP_C7_IRQ 0x4f
|
||||
#define GPP_C8_IRQ 0x50
|
||||
#define GPP_C9_IRQ 0x51
|
||||
#define GPP_C10_IRQ 0x52
|
||||
#define GPP_C11_IRQ 0x53
|
||||
#define GPP_C12_IRQ 0x54
|
||||
#define GPP_C13_IRQ 0x55
|
||||
#define GPP_C14_IRQ 0x56
|
||||
#define GPP_C15_IRQ 0x57
|
||||
#define GPP_C16_IRQ 0x58
|
||||
#define GPP_C17_IRQ 0x59
|
||||
#define GPP_C18_IRQ 0x5a
|
||||
#define GPP_C19_IRQ 0x5b
|
||||
#define GPP_C20_IRQ 0x5c
|
||||
#define GPP_C21_IRQ 0x5d
|
||||
#define GPP_C22_IRQ 0x5e
|
||||
#define GPP_C23_IRQ 0x5f
|
||||
/* Group D */
|
||||
#define GPP_D0_IRQ 0x60
|
||||
#define GPP_D1_IRQ 0x61
|
||||
#define GPP_D2_IRQ 0x62
|
||||
#define GPP_D3_IRQ 0x63
|
||||
#define GPP_D4_IRQ 0x64
|
||||
#define GPP_D5_IRQ 0x65
|
||||
#define GPP_D6_IRQ 0x66
|
||||
#define GPP_D7_IRQ 0x67
|
||||
#define GPP_D8_IRQ 0x68
|
||||
#define GPP_D9_IRQ 0x69
|
||||
#define GPP_D10_IRQ 0x6a
|
||||
#define GPP_D11_IRQ 0x6b
|
||||
#define GPP_D12_IRQ 0x6c
|
||||
#define GPP_D13_IRQ 0x6d
|
||||
#define GPP_D14_IRQ 0x6e
|
||||
#define GPP_D15_IRQ 0x6f
|
||||
#define GPP_D16_IRQ 0x70
|
||||
#define GPP_D17_IRQ 0x71
|
||||
#define GPP_D18_IRQ 0x72
|
||||
#define GPP_D19_IRQ 0x73
|
||||
#define GPP_D20_IRQ 0x74
|
||||
#define GPP_D21_IRQ 0x75
|
||||
#define GPP_D22_IRQ 0x76
|
||||
#define GPP_D23_IRQ 0x77
|
||||
/* Group E */
|
||||
#define GPP_E0_IRQ 0x18
|
||||
#define GPP_E1_IRQ 0x19
|
||||
#define GPP_E2_IRQ 0x1a
|
||||
#define GPP_E3_IRQ 0x1b
|
||||
#define GPP_E4_IRQ 0x1c
|
||||
#define GPP_E5_IRQ 0x1d
|
||||
#define GPP_E6_IRQ 0x1e
|
||||
#define GPP_E7_IRQ 0x1f
|
||||
#define GPP_E8_IRQ 0x20
|
||||
#define GPP_E9_IRQ 0x21
|
||||
#define GPP_E10_IRQ 0x22
|
||||
#define GPP_E11_IRQ 0x23
|
||||
#define GPP_E12_IRQ 0x24
|
||||
#define GPP_E13_IRQ 0x25
|
||||
#define GPP_E14_IRQ 0x26
|
||||
#define GPP_E15_IRQ 0x27
|
||||
#define GPP_E16_IRQ 0x28
|
||||
#define GPP_E17_IRQ 0x29
|
||||
#define GPP_E18_IRQ 0x2a
|
||||
#define GPP_E19_IRQ 0x2b
|
||||
#define GPP_E20_IRQ 0x2c
|
||||
#define GPP_E21_IRQ 0x2d
|
||||
#define GPP_E22_IRQ 0x2e
|
||||
#define GPP_E23_IRQ 0x2f
|
||||
/* Group F */
|
||||
#define GPP_F0_IRQ 0x30
|
||||
#define GPP_F1_IRQ 0x31
|
||||
#define GPP_F2_IRQ 0x32
|
||||
#define GPP_F3_IRQ 0x33
|
||||
#define GPP_F4_IRQ 0x34
|
||||
#define GPP_F5_IRQ 0x35
|
||||
#define GPP_F6_IRQ 0x36
|
||||
#define GPP_F7_IRQ 0x37
|
||||
#define GPP_F8_IRQ 0x38
|
||||
#define GPP_F9_IRQ 0x39
|
||||
#define GPP_F10_IRQ 0x3a
|
||||
#define GPP_F11_IRQ 0x3b
|
||||
#define GPP_F12_IRQ 0x3c
|
||||
#define GPP_F13_IRQ 0x3d
|
||||
#define GPP_F14_IRQ 0x3e
|
||||
#define GPP_F15_IRQ 0x3f
|
||||
#define GPP_F16_IRQ 0x40
|
||||
#define GPP_F17_IRQ 0x41
|
||||
#define GPP_F18_IRQ 0x42
|
||||
#define GPP_F19_IRQ 0x43
|
||||
#define GPP_F20_IRQ 0x44
|
||||
#define GPP_F21_IRQ 0x45
|
||||
#define GPP_F22_IRQ 0x46
|
||||
#define GPP_F23_IRQ 0x47
|
||||
/* Group G */
|
||||
#define GPP_G0_IRQ 0x6c
|
||||
#define GPP_G1_IRQ 0x6d
|
||||
#define GPP_G2_IRQ 0x6e
|
||||
#define GPP_G3_IRQ 0x6f
|
||||
#define GPP_G4_IRQ 0x70
|
||||
#define GPP_G5_IRQ 0x71
|
||||
#define GPP_G6_IRQ 0x72
|
||||
#define GPP_G7_IRQ 0x73
|
||||
/* Group GPD */
|
||||
#define GPD0_IRQ 0x60
|
||||
#define GPD1_IRQ 0x61
|
||||
#define GPD2_IRQ 0x62
|
||||
#define GPD3_IRQ 0x63
|
||||
#define GPD4_IRQ 0x64
|
||||
#define GPD5_IRQ 0x65
|
||||
#define GPD6_IRQ 0x66
|
||||
#define GPD7_IRQ 0x67
|
||||
#define GPD8_IRQ 0x68
|
||||
#define GPD9_IRQ 0x69
|
||||
#define GPD10_IRQ 0x6a
|
||||
#define GPD11_IRQ 0x6b
|
||||
/* Group H */
|
||||
#define GPP_H0_IRQ 0x48
|
||||
#define GPP_H1_IRQ 0x49
|
||||
#define GPP_H2_IRQ 0x4a
|
||||
#define GPP_H3_IRQ 0x4b
|
||||
#define GPP_H4_IRQ 0x4c
|
||||
#define GPP_H5_IRQ 0x4d
|
||||
#define GPP_H6_IRQ 0x4e
|
||||
#define GPP_H7_IRQ 0x4f
|
||||
#define GPP_H8_IRQ 0x50
|
||||
#define GPP_H9_IRQ 0x51
|
||||
#define GPP_H10_IRQ 0x52
|
||||
#define GPP_H11_IRQ 0x53
|
||||
#define GPP_H12_IRQ 0x54
|
||||
#define GPP_H13_IRQ 0x55
|
||||
#define GPP_H14_IRQ 0x56
|
||||
#define GPP_H15_IRQ 0x57
|
||||
#define GPP_H16_IRQ 0x58
|
||||
#define GPP_H17_IRQ 0x59
|
||||
#define GPP_H18_IRQ 0x5a
|
||||
#define GPP_H19_IRQ 0x5b
|
||||
#define GPP_H20_IRQ 0x5c
|
||||
#define GPP_H21_IRQ 0x5d
|
||||
#define GPP_H22_IRQ 0x5e
|
||||
#define GPP_H23_IRQ 0x5f
|
||||
/* Group I */
|
||||
#define GPP_I0_IRQ 0x18
|
||||
#define GPP_I1_IRQ 0x19
|
||||
#define GPP_I2_IRQ 0x1a
|
||||
#define GPP_I3_IRQ 0x1b
|
||||
#define GPP_I4_IRQ 0x1c
|
||||
#define GPP_I5_IRQ 0x1d
|
||||
#define GPP_I6_IRQ 0x1e
|
||||
#define GPP_I7_IRQ 0x1f
|
||||
#define GPP_I8_IRQ 0x20
|
||||
#define GPP_I9_IRQ 0x21
|
||||
#define GPP_I10_IRQ 0x22
|
||||
#define GPP_I11_IRQ 0x23
|
||||
#define GPP_I12_IRQ 0x24
|
||||
#define GPP_I13_IRQ 0x25
|
||||
#define GPP_I14_IRQ 0x26
|
||||
#define GPP_I15_IRQ 0x27
|
||||
#define GPP_I16_IRQ 0x28
|
||||
#define GPP_I17_IRQ 0x29
|
||||
#define GPP_I18_IRQ 0x2a
|
||||
#define GPP_I19_IRQ 0x2b
|
||||
#define GPP_I20_IRQ 0x2c
|
||||
#define GPP_I21_IRQ 0x2d
|
||||
#define GPP_I22_IRQ 0x2e
|
||||
#define GPP_I23_IRQ 0x2f
|
||||
/* Group J */
|
||||
#define GPP_J0_IRQ 0x30
|
||||
#define GPP_J1_IRQ 0x31
|
||||
#define GPP_J2_IRQ 0x32
|
||||
#define GPP_J3_IRQ 0x33
|
||||
#define GPP_J4_IRQ 0x34
|
||||
#define GPP_J5_IRQ 0x35
|
||||
#define GPP_J6_IRQ 0x36
|
||||
#define GPP_J7_IRQ 0x37
|
||||
#define GPP_J8_IRQ 0x38
|
||||
#define GPP_J9_IRQ 0x39
|
||||
#define GPP_J10_IRQ 0x3a
|
||||
#define GPP_J11_IRQ 0x3b
|
||||
#define GPP_J12_IRQ 0x3c
|
||||
#define GPP_J13_IRQ 0x3d
|
||||
#define GPP_J14_IRQ 0x3e
|
||||
#define GPP_J15_IRQ 0x3f
|
||||
#define GPP_J16_IRQ 0x40
|
||||
#define GPP_J17_IRQ 0x41
|
||||
#define GPP_J18_IRQ 0x42
|
||||
#define GPP_J19_IRQ 0x43
|
||||
#define GPP_J20_IRQ 0x44
|
||||
#define GPP_J21_IRQ 0x45
|
||||
#define GPP_J22_IRQ 0x46
|
||||
#define GPP_J23_IRQ 0x47
|
||||
/* Group K */
|
||||
#define GPP_K0_IRQ 0x48
|
||||
#define GPP_K1_IRQ 0x49
|
||||
#define GPP_K2_IRQ 0x4a
|
||||
#define GPP_K3_IRQ 0x4b
|
||||
#define GPP_K4_IRQ 0x4c
|
||||
#define GPP_K5_IRQ 0x4d
|
||||
#define GPP_K6_IRQ 0x4e
|
||||
#define GPP_K7_IRQ 0x4f
|
||||
#define GPP_K8_IRQ 0x50
|
||||
#define GPP_K9_IRQ 0x51
|
||||
#define GPP_K10_IRQ 0x52
|
||||
#define GPP_K11_IRQ 0x53
|
||||
#define GPP_K12_IRQ 0x54
|
||||
#define GPP_K13_IRQ 0x55
|
||||
#define GPP_K14_IRQ 0x56
|
||||
#define GPP_K15_IRQ 0x57
|
||||
#define GPP_K16_IRQ 0x58
|
||||
#define GPP_K17_IRQ 0x59
|
||||
#define GPP_K18_IRQ 0x5a
|
||||
#define GPP_K19_IRQ 0x5b
|
||||
#define GPP_K20_IRQ 0x5c
|
||||
#define GPP_K21_IRQ 0x5d
|
||||
#define GPP_K22_IRQ 0x5e
|
||||
#define GPP_K23_IRQ 0x5f
|
||||
/* Register defines. */
|
||||
#define GPIO_MISCCFG 0x10
|
||||
#define GPE_DW_SHIFT 8
|
||||
#define GPE_DW_MASK 0xfff00
|
||||
#define HOSTSW_OWN_REG_0 0xc0
|
||||
#define GPI_SMI_STS_0 0x180
|
||||
#define GPI_SMI_EN_0 0x1A0
|
||||
#define PAD_CFG_BASE 0x600
|
||||
|
||||
#define GPIORXSTATE_MASK 0x1
|
||||
#define GPIORXSTATE_SHIFT 1
|
||||
#endif
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2018 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_CANNONLAKE_GPIO_SOC_DEFS_CNP_H_H_
|
||||
#define _SOC_CANNONLAKE_GPIO_SOC_DEFS_CNP_H_H_
|
||||
|
||||
/*
|
||||
* Most of the fixed numbers and macros are based on the GPP groups.
|
||||
* The GPIO groups are accessed through register blocks called
|
||||
* communities.
|
||||
*/
|
||||
|
||||
#define GPP_A 0
|
||||
#define GPP_B 1
|
||||
#define GPP_C 2
|
||||
#define GPP_D 3
|
||||
#define GPP_G 4
|
||||
#define GPP_K 5
|
||||
#define GPP_H 6
|
||||
#define GPP_E 7
|
||||
#define GPP_F 8
|
||||
#define GPP_I 9
|
||||
#define GPP_J 0xA
|
||||
#define GPD 0xC
|
||||
#define GPIO_NUM_GROUPS 12
|
||||
#define GPIO_MAX_NUM_PER_GROUP 24
|
||||
|
||||
/*
|
||||
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
|
||||
*/
|
||||
|
||||
/* Group A */
|
||||
#define GPP_A0 0
|
||||
#define GPP_A1 1
|
||||
#define GPP_A2 2
|
||||
#define GPP_A3 3
|
||||
#define GPP_A4 4
|
||||
#define GPP_A5 5
|
||||
#define GPP_A6 6
|
||||
#define GPP_A7 7
|
||||
#define GPP_A8 8
|
||||
#define GPP_A9 9
|
||||
#define GPP_A10 10
|
||||
#define GPP_A11 11
|
||||
#define GPP_A12 12
|
||||
#define GPP_A13 13
|
||||
#define GPP_A14 14
|
||||
#define GPP_A15 15
|
||||
#define GPP_A16 16
|
||||
#define GPP_A17 17
|
||||
#define GPP_A18 18
|
||||
#define GPP_A19 19
|
||||
#define GPP_A20 20
|
||||
#define GPP_A21 21
|
||||
#define GPP_A22 22
|
||||
#define GPP_A23 23
|
||||
|
||||
/* Group B */
|
||||
#define GPP_B0 24
|
||||
#define GPP_B1 25
|
||||
#define GPP_B2 26
|
||||
#define GPP_B3 27
|
||||
#define GPP_B4 28
|
||||
#define GPP_B5 29
|
||||
#define GPP_B6 30
|
||||
#define GPP_B7 31
|
||||
#define GPP_B8 32
|
||||
#define GPP_B9 33
|
||||
#define GPP_B10 34
|
||||
#define GPP_B11 35
|
||||
#define GPP_B12 36
|
||||
#define GPP_B13 37
|
||||
#define GPP_B14 38
|
||||
#define GPP_B15 39
|
||||
#define GPP_B16 40
|
||||
#define GPP_B17 41
|
||||
#define GPP_B18 42
|
||||
#define GPP_B19 43
|
||||
#define GPP_B20 44
|
||||
#define GPP_B21 45
|
||||
#define GPP_B22 46
|
||||
#define GPP_B23 47
|
||||
|
||||
#define NUM_GPIO_COM0_PADS (GPP_B23 - GPP_A0 + 1)
|
||||
|
||||
/* Group C */
|
||||
#define GPP_C0 48
|
||||
#define GPP_C1 49
|
||||
#define GPP_C2 50
|
||||
#define GPP_C3 51
|
||||
#define GPP_C4 52
|
||||
#define GPP_C5 53
|
||||
#define GPP_C6 54
|
||||
#define GPP_C7 55
|
||||
#define GPP_C8 56
|
||||
#define GPP_C9 57
|
||||
#define GPP_C10 58
|
||||
#define GPP_C11 59
|
||||
#define GPP_C12 60
|
||||
#define GPP_C13 61
|
||||
#define GPP_C14 62
|
||||
#define GPP_C15 63
|
||||
#define GPP_C16 64
|
||||
#define GPP_C17 65
|
||||
#define GPP_C18 66
|
||||
#define GPP_C19 67
|
||||
#define GPP_C20 68
|
||||
#define GPP_C21 69
|
||||
#define GPP_C22 70
|
||||
#define GPP_C23 71
|
||||
|
||||
/* Group D */
|
||||
#define GPP_D0 72
|
||||
#define GPP_D1 73
|
||||
#define GPP_D2 74
|
||||
#define GPP_D3 75
|
||||
#define GPP_D4 76
|
||||
#define GPP_D5 77
|
||||
#define GPP_D6 78
|
||||
#define GPP_D7 79
|
||||
#define GPP_D8 80
|
||||
#define GPP_D9 81
|
||||
#define GPP_D10 82
|
||||
#define GPP_D11 83
|
||||
#define GPP_D12 84
|
||||
#define GPP_D13 85
|
||||
#define GPP_D14 86
|
||||
#define GPP_D15 87
|
||||
#define GPP_D16 88
|
||||
#define GPP_D17 89
|
||||
#define GPP_D18 90
|
||||
#define GPP_D19 91
|
||||
#define GPP_D20 92
|
||||
#define GPP_D21 93
|
||||
#define GPP_D22 94
|
||||
#define GPP_D23 95
|
||||
|
||||
/* Group G */
|
||||
#define GPP_G0 96
|
||||
#define GPP_G1 97
|
||||
#define GPP_G2 98
|
||||
#define GPP_G3 99
|
||||
#define GPP_G4 100
|
||||
#define GPP_G5 101
|
||||
#define GPP_G6 102
|
||||
#define GPP_G7 103
|
||||
|
||||
#define NUM_GPIO_COM1_PADS (GPP_G7 - GPP_C0 + 1)
|
||||
|
||||
/* Group K */
|
||||
#define GPP_K0 104
|
||||
#define GPP_K1 105
|
||||
#define GPP_K2 106
|
||||
#define GPP_K3 107
|
||||
#define GPP_K4 108
|
||||
#define GPP_K5 109
|
||||
#define GPP_K6 110
|
||||
#define GPP_K7 111
|
||||
#define GPP_K8 112
|
||||
#define GPP_K9 113
|
||||
#define GPP_K10 114
|
||||
#define GPP_K11 115
|
||||
#define GPP_K12 116
|
||||
#define GPP_K13 117
|
||||
#define GPP_K14 118
|
||||
#define GPP_K15 119
|
||||
#define GPP_K16 120
|
||||
#define GPP_K17 121
|
||||
#define GPP_K18 122
|
||||
#define GPP_K19 123
|
||||
#define GPP_K20 124
|
||||
#define GPP_K21 125
|
||||
#define GPP_K22 126
|
||||
#define GPP_K23 127
|
||||
|
||||
/* Group H */
|
||||
#define GPP_H0 128
|
||||
#define GPP_H1 129
|
||||
#define GPP_H2 130
|
||||
#define GPP_H3 131
|
||||
#define GPP_H4 132
|
||||
#define GPP_H5 133
|
||||
#define GPP_H6 134
|
||||
#define GPP_H7 135
|
||||
#define GPP_H8 136
|
||||
#define GPP_H9 137
|
||||
#define GPP_H10 138
|
||||
#define GPP_H11 139
|
||||
#define GPP_H12 140
|
||||
#define GPP_H13 141
|
||||
#define GPP_H14 142
|
||||
#define GPP_H15 143
|
||||
#define GPP_H16 144
|
||||
#define GPP_H17 145
|
||||
#define GPP_H18 146
|
||||
#define GPP_H19 147
|
||||
#define GPP_H20 148
|
||||
#define GPP_H21 149
|
||||
#define GPP_H22 150
|
||||
#define GPP_H23 151
|
||||
|
||||
/* Group E */
|
||||
#define GPP_E0 152
|
||||
#define GPP_E1 153
|
||||
#define GPP_E2 154
|
||||
#define GPP_E3 155
|
||||
#define GPP_E4 156
|
||||
#define GPP_E5 157
|
||||
#define GPP_E6 158
|
||||
#define GPP_E7 159
|
||||
#define GPP_E8 160
|
||||
#define GPP_E9 161
|
||||
#define GPP_E10 162
|
||||
#define GPP_E11 163
|
||||
#define GPP_E12 164
|
||||
|
||||
/* Group F */
|
||||
#define GPP_F0 165
|
||||
#define GPP_F1 166
|
||||
#define GPP_F2 167
|
||||
#define GPP_F3 168
|
||||
#define GPP_F4 169
|
||||
#define GPP_F5 170
|
||||
#define GPP_F6 171
|
||||
#define GPP_F7 172
|
||||
#define GPP_F8 173
|
||||
#define GPP_F9 174
|
||||
#define GPP_F10 175
|
||||
#define GPP_F11 176
|
||||
#define GPP_F12 177
|
||||
#define GPP_F13 178
|
||||
#define GPP_F14 179
|
||||
#define GPP_F15 180
|
||||
#define GPP_F16 181
|
||||
#define GPP_F17 182
|
||||
#define GPP_F18 183
|
||||
#define GPP_F19 184
|
||||
#define GPP_F20 185
|
||||
#define GPP_F21 186
|
||||
#define GPP_F22 187
|
||||
#define GPP_F23 188
|
||||
|
||||
#define NUM_GPIO_COM3_PADS (GPP_F23 - GPP_K0 + 1)
|
||||
|
||||
/* Group I */
|
||||
#define GPP_I0 189
|
||||
#define GPP_I1 190
|
||||
#define GPP_I2 191
|
||||
#define GPP_I3 192
|
||||
#define GPP_I4 193
|
||||
#define GPP_I5 194
|
||||
#define GPP_I6 195
|
||||
#define GPP_I7 196
|
||||
#define GPP_I8 197
|
||||
#define GPP_I9 198
|
||||
#define GPP_I10 199
|
||||
#define GPP_I11 200
|
||||
#define GPP_I12 201
|
||||
#define GPP_I13 202
|
||||
#define GPP_I14 203
|
||||
|
||||
/* Group J */
|
||||
#define GPP_J0 204
|
||||
#define GPP_J1 205
|
||||
#define GPP_J2 206
|
||||
#define GPP_J3 207
|
||||
#define GPP_J4 208
|
||||
#define GPP_J5 209
|
||||
#define GPP_J6 210
|
||||
#define GPP_J7 211
|
||||
#define GPP_J8 212
|
||||
#define GPP_J9 213
|
||||
#define GPP_J10 214
|
||||
#define GPP_J11 215
|
||||
|
||||
#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1)
|
||||
|
||||
/* Group GPD */
|
||||
#define GPD0 216
|
||||
#define GPD1 217
|
||||
#define GPD2 218
|
||||
#define GPD3 219
|
||||
#define GPD4 220
|
||||
#define GPD5 221
|
||||
#define GPD6 222
|
||||
#define GPD7 223
|
||||
#define GPD8 224
|
||||
#define GPD9 225
|
||||
#define GPD10 226
|
||||
#define GPD11 227
|
||||
|
||||
#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
|
||||
|
||||
#define TOTAL_PADS (GPD11 + 1)
|
||||
#endif
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2017 Intel Corporation.
|
||||
* Copyright (C) 2017-2018 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -116,6 +116,20 @@
|
|||
#define GPE0_DWX_MASK 0xf
|
||||
#define GPE0_DW_SHIFT(x) (4*(x))
|
||||
|
||||
#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
|
||||
#define PMC_GPP_A 0x0
|
||||
#define PMC_GPP_B 0x1
|
||||
#define PMC_GPP_C 0x2
|
||||
#define PMC_GPP_D 0x3
|
||||
#define PMC_GPP_E 0x7
|
||||
#define PMC_GPP_F 0x8
|
||||
#define PMC_GPP_G 0x4
|
||||
#define PMC_GPP_H 0x6
|
||||
#define PMC_GPP_I 0x9
|
||||
#define PMC_GPP_J 0xA
|
||||
#define PMC_GPP_K 0x5
|
||||
#define PMC_GPD 0xC
|
||||
#else
|
||||
#define PMC_GPP_A 0x0
|
||||
#define PMC_GPP_B 0x1
|
||||
#define PMC_GPP_C 0xD
|
||||
|
|
@ -125,6 +139,7 @@
|
|||
#define PMC_GPP_G 0x2
|
||||
#define PMC_GPP_H 0x6
|
||||
#define PMC_GPD 0xA
|
||||
#endif
|
||||
|
||||
#define GBLRST_CAUSE0 0x1924
|
||||
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
|
|||
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
|
||||
m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
|
||||
m_cfg->SaGv = config->SaGv;
|
||||
if (IS_ENABLED(CONFIG_CANNONLAKE_SOC_PCH_H))
|
||||
if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H))
|
||||
m_cfg->UserBd = BOARD_TYPE_DESKTOP;
|
||||
else
|
||||
m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
|
||||
|
|
|
|||
Loading…
Reference in New Issue