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zero warning days. Move RAMTOP and RAMBASE together. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-14 18:59:42 +00:00 committed by Stefan Reinauer
parent 97b21be8c7
commit 523ebd927d
18 changed files with 62 additions and 116 deletions
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4
src/Kconfig
View File

@ -152,10 +152,6 @@ config MMCONF_SUPPORT
bool
default n
config RAMTOP
hex
default 0x200000
config ATI_RAGE_XL
bool

4
src/arch/i386/Kconfig
View File

@ -30,6 +30,10 @@ config RAMBASE
hex
default 0x100000
config RAMTOP
hex
default 0x200000
config STACK_SIZE
hex
default 0x8000

13
src/mainboard/kontron/kt690/mainboard.c
View File

@ -22,10 +22,11 @@
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <../southbridge/amd/sb600/sb600.h>
#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@ -185,11 +186,8 @@ static void set_thermal_config(void)
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*************************************************/
void kt690_enable(device_t dev)
static void kt690_enable(device_t dev)
{
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
@ -229,8 +227,8 @@ void kt690_enable(device_t dev)
/* TODO: TOP_MEM2 */
#else
uma_memory_size = 0x8000000; /* 128M recommended UMA */
uma_memory_base = 0x38000000; /* 1GB system memory supposed */
uma_memory_size = 0x0;
uma_memory_base = 0x0;
#endif
enable_onboard_nic();
@ -249,6 +247,7 @@ int add_mainboard_resources(struct lb_memory *mem)
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
return 0;
}
struct chip_operations mainboard_ops = {

25
src/mainboard/msi/ms9282/romstage.c
View File

@ -135,8 +135,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@ -147,7 +145,6 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
}
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
@ -156,19 +153,19 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
#endif
};
static const uint16_t spd_addr[] = {
// Node 0
RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
// node 1
RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
};
unsigned bsp_apicid = 0;
unsigned bsp_apicid = 0;
int needs_reset;
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p ;
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */

10
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -145,8 +145,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@ -161,21 +159,21 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;

33
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -85,12 +85,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static int smbus_send_byte_one(unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
}
static void dump_smbus_registers(void)
static inline void dump_smbus_registers(void)
{
u32 device;
@ -119,17 +114,22 @@ static void dump_smbus_registers(void)
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* We don't do any switching yet.
#if 0
/* We don't do any switching yet. */
#define SMBUS_SWITCH1 0x48
#define SMBUS_SWITCH2 0x49
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_SWITCH1, device);
smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
*/
/* nothing to do */
#endif
}
#if 0
static int smbus_send_byte_one(unsigned device, unsigned char val)
{
return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
}
/*
static inline void change_i2c_mux(unsigned device)
{
#define SMBUS_SWITCH1 0x48
@ -146,7 +146,7 @@ static inline void change_i2c_mux(unsigned device)
print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
dump_smbus_registers();
}
*/
#endif
static inline int spd_read_byte(unsigned device, unsigned address)
{
@ -188,8 +188,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
u32 value;
uint32_t dword;
uint8_t byte;
@ -208,7 +206,6 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
}
/* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
@ -222,20 +219,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
memory on each CPU must be an exact match.
*/
static const uint16_t spd_addr[] = {
// Node 0
RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
#endif
};
struct sys_info *sysinfo =
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;

10
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -133,8 +133,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
enable_smbus();
@ -152,21 +150,21 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;

2
src/mainboard/supermicro/h8dmr_fam10/romstage.c
View File

@ -116,8 +116,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
enable_smbus();

4
src/mainboard/supermicro/h8qme_fam10/romstage.c
View File

@ -120,8 +120,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
enable_smbus();
@ -149,7 +147,7 @@ static void sio_setup(void)
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
void write_GPIO(void)
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
pnp_set_logical_device(GPIO1_DEV);

4
src/mainboard/technexion/tim5690/Kconfig
View File

@ -110,7 +110,3 @@ config HEAP_SIZE
default 0x4000
depends on BOARD_TECHNEXION_TIM5690
config RAMBASE
hex
default 0x100000
depends on BOARD_TECHNEXION_TIM5690

25
src/mainboard/technexion/tim5690/mainboard.c
View File

@ -22,11 +22,12 @@
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <../southbridge/amd/sb600/sb600.h>
#include <../superio/ite/it8712f/it8712f.h>
#include <southbridge/amd/sb600/sb600.h>
#include <superio/ite/it8712f/it8712f.h>
#include "chip.h"
#include "tn_post_code.h"
#include "vgabios.h"
@ -57,7 +58,6 @@
#define TV_MODE_09 0x09 /* SCART-RGB */
#define TV_MODE_NO 0xff /* No TV Support */
/* The base address is 0x2e or 0x4e, depending on config bytes. */
#define SIO_BASE 0x2e
#define SIO_INDEX SIO_BASE
@ -75,12 +75,8 @@
#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
@ -88,15 +84,8 @@ extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
/* previous
*/
void tim5690_enable(device_t dev);
int add_mainboard_resources(struct lb_memory *mem);
uint64_t uma_memory_base, uma_memory_size;
/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
LDN the register belongs to, before you can access the register. */
static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
@ -126,7 +115,6 @@ static void it8712f_exit_conf(void)
it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
}
/* set thermal config
*/
static void set_thermal_config(void)
@ -236,7 +224,7 @@ void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
* enable the dedicated function in tim5690 board.
* This function called early than rs690_enable.
*************************************************/
void tim5690_enable(device_t dev)
static void tim5690_enable(device_t dev)
{
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
@ -312,6 +300,7 @@ int add_mainboard_resources(struct lb_memory *mem)
uma_memory_base, uma_memory_size);
#endif
technexion_post_code(LED_MESSAGE_FINISH);
return 0;
}
struct chip_operations mainboard_ops = {

7
src/mainboard/technexion/tim8690/mainboard.c
View File

@ -22,6 +22,7 @@
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
@ -145,11 +146,8 @@ static void set_thermal_config(void)
* enable the dedicated function in tim8690 board.
* This function called early than rs690_enable.
*************************************************/
void tim8690_enable(device_t dev)
static void tim8690_enable(device_t dev)
{
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
@ -208,6 +206,7 @@ int add_mainboard_resources(struct lb_memory *mem)
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
return 0;
}
struct chip_operations mainboard_ops = {

1
src/mainboard/tyan/s2735/reset.c
View File

@ -1,3 +1,4 @@
#include <reset.h>
void i82801ex_hard_reset(void);
/* FIXME: There's another hard_reset() in romstage.c. Why? */

15
src/mainboard/tyan/s2735/romstage.c
View File

@ -32,15 +32,6 @@ static void hard_reset(void)
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@ -61,14 +52,10 @@ void main(unsigned long bist)
},
};
unsigned cpu_reset = 0;
if (bist == 0) {
enable_lapic();
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@ -76,8 +63,6 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// setup_s2735_resource_map();
if(bios_reset_detected()) {
hard_reset();
}

10
src/mainboard/tyan/s2912/romstage.c
View File

@ -143,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@ -160,21 +158,21 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;

2
src/mainboard/tyan/s2912_fam10/romstage.c
View File

@ -126,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@ -142,7 +141,6 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
}
#include "spd_addr.h"

4
src/mainboard/via/epia-cn/romstage.c
View File

@ -48,7 +48,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void)
{
device_t dev;
u8 reg;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
@ -84,9 +83,6 @@ static const struct mem_controller ctrl = {
void main(unsigned long bist)
{
unsigned long x;
device_t dev;
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);

5
src/southbridge/via/vt8237r/vt8237r_usb.c
View File

@ -30,16 +30,15 @@ u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800};
static void usb_i_init(struct device *dev)
{
#if CONFIG_EPIA_VT8237R_INIT
u8 reg8;
printk(BIOS_DEBUG, "Entering %s\n", __func__);
printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
reg8 = pci_read_config8(dev, 0x04);
printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8);
reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, 0x04, reg8);