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mb/google/hatch: Implement touchscreen power sequencing 

For touchscreens on hatch variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit).

BUG=b:121309055
TEST=tested with rest of patch train

Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2022-03-28 23:19:45 -05:00 committed by Martin L Roth
parent c0edb925e6
commit 525c61f74e
10 changed files with 203 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/mainboard/google/hatch/variants/akemi/gpio.c
View File

@ -22,6 +22,10 @@ static const struct pad_config ssd_sku_gpio_table[] = {
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
@ -79,6 +83,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
@ -178,3 +186,18 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/dratini/gpio.c
View File

@ -16,6 +16,10 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A19, NONE),
/* C12 : FPMCU_PCH_BOOT1 */
PAD_CFG_GPO(GPP_C12, 0, DEEP),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
@ -156,3 +160,18 @@ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
*num = ARRAY_SIZE(default_sleep_gpio_table);
return default_sleep_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/hatch/gpio.c
View File

@ -25,6 +25,10 @@ static const struct pad_config gpio_table[] = {
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
};
const struct pad_config *override_gpio_table(size_t *num)
@ -76,3 +80,18 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/helios/gpio.c
View File

@ -40,8 +40,12 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_D7, NONE),
/* D8 : ISH_I2C1_SCL ==> NC */
PAD_NC(GPP_D8, NONE),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D10 : ISH_SPI_CLK ==> EN_PP3300_PP1800_FP */
PAD_CFG_GPO(GPP_D10, 0, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* D16 : USI_INT_L */
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
/* D21 : SPI1_IO2 ==> NC */
@ -168,3 +172,18 @@ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
*num = ARRAY_SIZE(default_sleep_gpio_table);
return default_sleep_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/jinlon/gpio.c
View File

@ -20,6 +20,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* D4 : Camera Privacy Status */
PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* E0 : View Angle Management */
PAD_CFG_GPO(GPP_E0, 0, DEEP),
/* F3 : MEM_STRAP_3 */
@ -136,3 +140,18 @@ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
*num = ARRAY_SIZE(default_sleep_gpio_table);
return default_sleep_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

27
src/mainboard/google/hatch/variants/kindred/gpio.c
View File

@ -24,6 +24,10 @@ static const struct pad_config ssd_sku_gpio_table[] = {
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
@ -73,6 +77,10 @@ static const struct pad_config emmc_sku_gpio_table[] = {
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
/* A12 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* E1 : M2_SSD_PEDET ==> NC */
PAD_NC(GPP_E1, NONE),
/* E4 : M2_SSD_PE_WAKE_ODL ==> NC */
@ -134,6 +142,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF2),
/* A12 : FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* C15 : WWAN_DPR_SAR_ODL
*
* TODO: Driver doesn't use this pin as of now. In case driver starts
@ -236,3 +248,18 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/kohaku/gpio.c
View File

@ -29,13 +29,15 @@ static const struct pad_config gpio_table[] = {
/* C7 : PEN_IRQ_OD_L */
PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
/* C12 : EN_PP3300_TSP_DX */
PAD_CFG_GPO(GPP_C12, 0, DEEP),
PAD_CFG_GPO(GPP_C12, 1, DEEP),
/* C13 : EC_PCH_INT_L - needs to wake the system */
PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
/* C15 : EN_PP3300_DIG_DX */
PAD_CFG_GPO(GPP_C15, 0, DEEP),
/* C23 : UART2_CTS# ==> NC */
PAD_NC(GPP_C23, NONE),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_C12, 1, DEEP),
/* D16 : TOUCHSCREEN_INT_L */
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
/* E23 : GPP_E23 ==> NC */
@ -173,3 +175,18 @@ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
*num = ARRAY_SIZE(default_sleep_gpio_table);
return default_sleep_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* C12 : EN_PP3300_TSP_DX */
PAD_CFG_GPO(GPP_C12, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/mushu/gpio.c
View File

@ -25,6 +25,10 @@ static const struct pad_config gpio_table[] = {
* using this pin, expose this pin to driver.
*/
PAD_CFG_GPO(GPP_C15, 1, DEEP),
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* H3 : SPKR_PA_EN */
PAD_CFG_GPO(GPP_H3, 0, DEEP),
/* H22 : BOMACO_EN */
@ -80,3 +84,18 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

19
src/mainboard/google/hatch/variants/nightfury/gpio.c
View File

@ -29,12 +29,14 @@ static const struct pad_config gpio_table[] = {
/* C1 : NC */
PAD_NC(GPP_C1, NONE),
/* C12 : EN_PP3300_TSP_DX */
PAD_CFG_GPO(GPP_C12, 0, DEEP),
PAD_CFG_GPO(GPP_C12, 1, DEEP),
/* C13 : EC_PCH_INT_L - needs to wake the system */
PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
/* C23 : UART2_CTS# ==> NC */
PAD_NC(GPP_C23, NONE),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* D16 : TOUCHSCREEN_INT_L */
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
/* D19 : DMIC_CLK_0_SNDW4_CLK */
@ -171,3 +173,18 @@ const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num)
*num = ARRAY_SIZE(default_sleep_gpio_table);
return default_sleep_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreen, hold in reset */
/* C12 : EN_PP3300_TSP_DX */
PAD_CFG_GPO(GPP_C12, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

23
src/mainboard/google/hatch/variants/palkia/gpio.c
View File

@ -42,8 +42,12 @@ static const struct pad_config gpio_table[] = {
/* D4 : USI_BASE_REPORT_EN */
PAD_CFG_GPO(GPP_D4, 0, DEEP),
/* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D10 : GPP_D10 ==> EN_PP3300_DX_BASE_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D10, 0, DEEP),
PAD_CFG_GPO(GPP_D10, 1, DEEP),
/* D15 : GPP_D15 ==> TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 1, DEEP),
/* D16 : USI_INT_L */
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
@ -142,3 +146,20 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIOs needed to be set in romstage. */
static const struct pad_config romstage_gpio_table[] = {
/* Enable touchscreens, hold in reset */
/* D9 : EN_PP3300_DX_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D9, 1, DEEP),
/* D10 : EN_PP3300_DX_BASE_TOUCHSCREEN */
PAD_CFG_GPO(GPP_D10, 1, DEEP),
/* D15 : TOUCHSCREEN_RST_L */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
};
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}