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rockchip: spi: Set rxd sample delay when using high speed 

At higher SPI bus speeds the SPI RX value is not available in time for
sampling at the normal time. Add a delay to ensure that we read the
correct data.

The value of 40ns is chosen arbitrarily. In my testing I can use a sample
delay of 1 even at 24MHz. But since it is not necessary, I have left that
case alone. It kicks in at 25MHz and up.

BUG=chrome-os-partner:56556
BRANCH=none
TEST=boot on gru and see no change at current speed

Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7
Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782
Original-Signed-off-by: Simon Glass <sjg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381311
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Simon Glass <sjg@google.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16707
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Simon Glass 2016-09-05 11:04:50 -06:00 committed by Patrick Georgi
parent 7feb86b26b
commit 52669fc4dc
2 changed files with 17 additions and 4 deletions
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3
src/soc/rockchip/common/include/soc/spi.h
View File

@ -199,4 +199,7 @@ check_member(rockchip_spi, rxdr, 0x800);
void rockchip_spi_init(unsigned int bus, unsigned int speed_hz);
/* Set the receive sample delay in nanoseconds */
void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns);
#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H */

18
src/soc/rockchip/common/spi.c
View File

@ -32,7 +32,7 @@ struct rockchip_spi_slave {
};
#define SPI_TIMEOUT_US 1000
#define SPI_SRCCLK_HZ (99*MHz)
#define SPI_SRCCLK_HZ (198*MHz)
#define SPI_FIFO_DEPTH 32
static struct rockchip_spi_slave rockchip_spi_slaves[] = {
@ -152,9 +152,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
/* Byte and Halfword Transform */
ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET);
/* Rxd Sample Delay */
ctrlr0 |= (0 << SPI_RXDSD_OFFSET);
/* Frame Format */
ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET);
@ -165,6 +162,19 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
write32(&regs->rxftlr, SPI_FIFO_DEPTH / 2 - 1);
}
void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns)
{
assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
unsigned int rsd;
/* Rxd Sample Delay */
rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8);
assert(rsd >= 0 && rsd <= 3);
clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET,
rsd << SPI_RXDSD_OFFSET);
}
int spi_claim_bus(struct spi_slave *slave)
{
spi_cs_activate(slave);