rockchip: spi: Set rxd sample delay when using high speed
At higher SPI bus speeds the SPI RX value is not available in time for sampling at the normal time. Add a delay to ensure that we read the correct data. The value of 40ns is chosen arbitrarily. In my testing I can use a sample delay of 1 even at 24MHz. But since it is not necessary, I have left that case alone. It kicks in at 25MHz and up. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see no change at current speed Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7 Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381311 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16707 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -199,4 +199,7 @@ check_member(rockchip_spi, rxdr, 0x800);
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void rockchip_spi_init(unsigned int bus, unsigned int speed_hz);
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void rockchip_spi_init(unsigned int bus, unsigned int speed_hz);
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/* Set the receive sample delay in nanoseconds */
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void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns);
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#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H */
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#endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H */
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@ -32,7 +32,7 @@ struct rockchip_spi_slave {
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};
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};
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#define SPI_TIMEOUT_US 1000
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#define SPI_TIMEOUT_US 1000
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#define SPI_SRCCLK_HZ (99*MHz)
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#define SPI_SRCCLK_HZ (198*MHz)
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#define SPI_FIFO_DEPTH 32
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#define SPI_FIFO_DEPTH 32
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static struct rockchip_spi_slave rockchip_spi_slaves[] = {
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static struct rockchip_spi_slave rockchip_spi_slaves[] = {
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@ -152,9 +152,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
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/* Byte and Halfword Transform */
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/* Byte and Halfword Transform */
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ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET);
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ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET);
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/* Rxd Sample Delay */
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ctrlr0 |= (0 << SPI_RXDSD_OFFSET);
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/* Frame Format */
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/* Frame Format */
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ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET);
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ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET);
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@ -165,6 +162,19 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
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write32(®s->rxftlr, SPI_FIFO_DEPTH / 2 - 1);
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write32(®s->rxftlr, SPI_FIFO_DEPTH / 2 - 1);
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}
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}
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void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns)
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{
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assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
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struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
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unsigned int rsd;
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/* Rxd Sample Delay */
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rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8);
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assert(rsd >= 0 && rsd <= 3);
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clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET,
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rsd << SPI_RXDSD_OFFSET);
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}
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int spi_claim_bus(struct spi_slave *slave)
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int spi_claim_bus(struct spi_slave *slave)
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{
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{
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spi_cs_activate(slave);
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spi_cs_activate(slave);
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