src/soc: Fix various typos

These typos were found through manual review and grep.

Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/soc/amd/stoneyridge/include/soc/northbridge.h

@@ -80,7 +80,7 @@ enum {
 void smm_region_info(void **start, size_t *size);
 /*
  * Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure.
+ * 0 on success, < 0 on failure.
  */
 int smm_subregion(int sub, void **start, size_t *size);
 void domain_enable_resources(device_t dev);

src/soc/amd/stoneyridge/southbridge.c

@@ -75,7 +75,7 @@ void SetFchMidParams(FCH_INTERFACE *params)
 
 /*
  * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
- * provides a visible association with the index, therefor helping
+ * provides a visible association with the index, therefore helping
  * maintainability of table. If a new index/name is defined in
  * amd_pci_int_defs.h, just add the pair at the end of this table.
  * Order is not important.

src/soc/broadcom/cygnus/hw_init.c

@@ -106,7 +106,7 @@ static void crmu_ns_config(void)
 	 *
 	 * NOTE: In the future, we might want to protect particular CRMU
 	 * sub-blocks to allow SECURE access only. That can be done by
-	 * programing the CRMU IPROC address range registers. Up to 4 access
+	 * programming the CRMU IPROC address range registers. Up to 4 access
 	 * windows can be created
 	 */
 	write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,

src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h

@@ -218,7 +218,7 @@
 #define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x000004a0 /* Read enable bit-clock cycle delay control register */
 #define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x000004a4 /* Write leveling bit-clock cycle delay control register */
 #define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL  0x000004b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo addresss pointer register */
+#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo address pointer register */
 #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x000004b8 /* Read fifo data register */
 #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004bc /* Read fifo dm/dbi register */
 #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004c0 /* Read fifo status register */
@@ -284,7 +284,7 @@
 #define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x000006a0 /* Read enable bit-clock cycle delay control register */
 #define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x000006a4 /* Write leveling bit-clock cycle delay control register */
 #define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL  0x000006b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo addresss pointer register */
+#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo address pointer register */
 #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x000006b8 /* Read fifo data register */
 #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006bc /* Read fifo dm/dbi register */
 #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006c0 /* Read fifo status register */
@@ -7729,7 +7729,7 @@
 #define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
 
 /***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
+ *READ_FIFO_ADDR - Read fifo address pointer register
  ***************************************************************************/
 /* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
 #define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_MASK   0xfffffff8
@@ -10483,7 +10483,7 @@
 #define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
 
 /***************************************************************************
- *READ_FIFO_ADDR - Read fifo addresss pointer register
+ *READ_FIFO_ADDR - Read fifo address pointer register
  ***************************************************************************/
 /* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
 #define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_MASK   0xfffffff8

src/soc/imgtec/pistachio/ddr2_init.c

@@ -288,7 +288,7 @@ int init_ddr2(void)
 	 */
 	write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x00000012);
 	/*
-	 * TRC : Min. ROW cylce time
+	 * TRC : Min. ROW cycle time
 	 * Range 11 to 31: 57.5ns / 2.5ns = 23d Playing safe 24
 	 */
 	write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000018);

src/soc/imgtec/pistachio/ddr3_init.c

@@ -303,7 +303,7 @@ int init_ddr3(void)
 	write32(DDR_PCTL + DDR_PCTL_TCWL_OFFSET, 0x00000005);
 	/* TRAS : Activate to Precharge cmd time  15 45ns / 2.5ns = 18d */
 	write32(DDR_PCTL + DDR_PCTL_TRAS_OFFSET, 0x0000000F);
-	/* TRC : Min. ROW cylce time  21
+	/* TRC : Min. ROW cycle time  21
 	 * 57.5ns / 2.5ns = 23d Playing safe 24
 	 */
 	write32(DDR_PCTL + DDR_PCTL_TRC_OFFSET, 0x00000015);
@@ -428,7 +428,7 @@ int init_ddr3(void)
 	 */
 	write32(DDR_PCTL + DDR_PCTL_DFIODTCFG1_OFFSET, 0x060600000);
 
-	/* Memory initilization */
+	/* Memory initialization */
 	/* MCMD : PREA, Addr 0 Bank 0 Rank 0 Del 0
 	 * 3:0 cmd_opcode PREA 00001
 	 * 16:4 cmd_addr 0

src/soc/intel/apollolake/include/soc/meminit.h

@@ -76,7 +76,7 @@ enum {
  * and LOW for ODT_B, choose ODT_AB_HIGH_LOW.
  *
  * Note that the enum values correspond to the interpreted UPD fields
- * witihn Ch[3:0]_OdtConfig parameters.
+ * within Ch[3:0]_OdtConfig parameters.
 */
 enum {
 	ODT_A_B_HIGH_LOW = 0 << 1,

src/soc/intel/apollolake/meminit.c

@@ -130,10 +130,10 @@ static void enable_logical_chan0(FSP_M_CONFIG *cfg,
 	/*
 	 * CH0_DQB byte lanes in the bit swizzle configuration field are
 	 * not 1:1. The mapping within the swizzling field is:
-	 *   indicies [0:7]   - byte lane 1 (DQS1) DQ[8:15]
-	 *   indicies [8:15]  - byte lane 0 (DQS0) DQ[0:7]
-	 *   indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
-	 *   indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+	 *   indices [0:7]   - byte lane 1 (DQS1) DQ[8:15]
+	 *   indices [8:15]  - byte lane 0 (DQS0) DQ[0:7]
+	 *   indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+	 *   indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
 	 */
 	chan = &scfg->phys[LP4_PHYS_CH0B];
 	memcpy(&cfg->Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);
@@ -175,10 +175,10 @@ static void enable_logical_chan1(FSP_M_CONFIG *cfg,
 	/*
 	 * CH1_DQB byte lanes in the bit swizzle configuration field are
 	 * not 1:1. The mapping within the swizzling field is:
-	 *   indicies [0:7]   - byte lane 1 (DQS1) DQ[8:15]
-	 *   indicies [8:15]  - byte lane 0 (DQS0) DQ[0:7]
-	 *   indicies [16:23] - byte lane 3 (DQS3) DQ[24:31]
-	 *   indicies [24:31] - byte lane 2 (DQS2) DQ[16:23]
+	 *   indices [0:7]   - byte lane 1 (DQS1) DQ[8:15]
+	 *   indices [8:15]  - byte lane 0 (DQS0) DQ[0:7]
+	 *   indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
+	 *   indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
 	 */
 	chan = &scfg->phys[LP4_PHYS_CH1B];
 	memcpy(&cfg->Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1], sz);

src/soc/intel/apollolake/romstage.c

@@ -87,7 +87,7 @@ static void soc_early_romstage_init(void)
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 	};
 
-	/* Set Fixed MMIO addresss into PCI configuration space */
+	/* Set Fixed MMIO address into PCI configuration space */
 	sa_set_pci_bar(soc_fixed_pci_resources,
 			ARRAY_SIZE(soc_fixed_pci_resources));
 

src/soc/intel/apollolake/systemagent.c

@@ -27,7 +27,7 @@
 /*
  * SoC implementation
  *
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
  * controller.
  */
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)

src/soc/intel/cannonlake/include/soc/bootblock.h

@@ -18,11 +18,11 @@
 
 #include <intelblocks/systemagent.h>
 
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
 void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
 void pch_early_init(void);
 void pch_early_iorange_init(void);
 void report_platform_info(void);

src/soc/intel/cannonlake/include/soc/vr_config.h

@@ -26,7 +26,7 @@ struct vr_config {
 	 * for that domain. */
 	uint8_t vr_config_enable;
 
-	/* Power State X current cuttof in 1/4 Amp increments
+	/* Power State X current cutoff in 1/4 Amp increments
 	 * Range is 0-128A */
 	uint16_t psi1threshold;
 	uint16_t psi2threshold;

src/soc/intel/cannonlake/romstage/systemagent.c

@@ -34,12 +34,12 @@ void systemagent_early_init(void)
 		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
 	};
 
-	/* Set Fixed MMIO addresss into PCI configuration space */
+	/* Set Fixed MMIO address into PCI configuration space */
 	sa_set_pci_bar(soc_fixed_pci_resources,
 		       ARRAY_SIZE(soc_fixed_pci_resources));
-	/* Set Fixed MMIO addresss into MCH base address */
+	/* Set Fixed MMIO address into MCH base address */
 	sa_set_mch_bar(soc_fixed_mch_resources,
 		       ARRAY_SIZE(soc_fixed_mch_resources));
-	/* Enable PAM regisers */
+	/* Enable PAM registers */
 	enable_pam_region();
 }

src/soc/intel/cannonlake/systemagent.c

@@ -25,7 +25,7 @@
 /*
  * SoC implementation
  *
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
  * controller.
  */
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -389,7 +389,7 @@ find_llc_subleaf:
 	 * Maximizing RO cacheability while locking in the CAR to a
 	 * single way since that particular way won't be victim candidate
 	 * for evictions.
-	 * This has been done after programing LLC_WAY_MASK_1 MSR
+	 * This has been done after programming LLC_WAY_MASK_1 MSR
 	 * with desired LLC way as mentioned below.
 	 *
 	 * Hence create Code and Data Size as per request

src/soc/intel/common/block/cse/cse.c

@@ -31,7 +31,7 @@
 
 /* Wait up to 15 sec for HECI to get ready */
 #define HECI_DELAY_READY	(15 * 1000)
-/* Wait up to 100 usec between circullar buffer polls */
+/* Wait up to 100 usec between circular buffer polls */
 #define HECI_DELAY		100
 /* Wait up to 5 sec for CSE to chew something we sent */
 #define HECI_SEND_TIMEOUT	(5 * 1000)
@@ -341,7 +341,7 @@ heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr)
 
 		/*
 		 * Fragment the message into smaller messages not exceeding
-		 * useful circullar buffer length. Mark last message complete.
+		 * useful circular buffer length. Mark last message complete.
 		 */
 		do {
 			hdr = MIN(max_length, remaining)

src/soc/intel/common/block/include/intelblocks/acpi.h

@@ -44,7 +44,7 @@ unsigned long southbridge_write_acpi_tables(device_t device,
 					    struct acpi_rsdp *rsdp);
 
 /*
- * Craetes acpi gnvs and adds it to the DSDT table.
+ * Creates acpi gnvs and adds it to the DSDT table.
  * GNVS creation is chipset specific and is done in soc specific acpi.c file.
  */
 void southbridge_inject_dsdt(device_t device);
@@ -84,7 +84,7 @@ void generate_t_state_entries(int core, int cores_per_package);
 /*
  * soc specific power states generation. We need this to be defined by soc
  * as the state generations varies in chipsets e.g. APL generates T and P
- * states while SKL generates  * P state only depening on a devicetree config
+ * states while SKL generates  * P state only depending on a devicetree config
  */
 void soc_power_states_generation(int core_id, int cores_per_package);
 

src/soc/intel/common/block/include/intelblocks/lpc_lib.h

@@ -69,14 +69,14 @@ void lpc_close_pmio_windows(void);
 void lpc_open_mmio_window(uintptr_t base, size_t size);
 /* Returns true if given window is decoded to LPC via a fixed range. */
 bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
-/* Init SoC Spcific LPC features. Common definition will be weak and
+/* Init SoC Specific LPC features. Common definition will be weak and
 each soc will need to define the init. */
 void lpc_soc_init(struct device *dev);
 /* Fill up LPC IO resource structure inside SoC directory */
 void pch_lpc_soc_fill_io_resources(struct device *dev);
 /* Init LPC GPIO pads */
 void lpc_configure_pads(void);
-/* Get SoC speicific MMIO ranges */
+/* Get SoC specific MMIO ranges */
 const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);
 /* Set LPC BIOS Control BILD bit. */
 void lpc_set_bios_interface_lock_down(void);
@@ -97,7 +97,7 @@ void lpc_enable_pci_clk_cntl(void);
 void lpc_io_setup_comm_a_b(void);
 /* Enable PCH LPC by setting up generic decode range registers. */
 void pch_enable_lpc(void);
-/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */
+/* Retrieve and setup SoC specific PCH LPC interrupt routing. */
 void soc_pch_pirq_init(const struct device *dev);
 /* Get SoC's generic IO decoder range register settings. */
 void soc_get_gen_io_dec_range(const struct device *dev,

src/soc/intel/common/block/include/intelblocks/pmclib.h

@@ -37,7 +37,7 @@ uint32_t soc_get_smi_status(uint32_t generic_sts);
 /*
  * This function is specific to soc and is defined as weak in common
  * pmclib file. SOC code can implement it for any special condition
- * specific to the soc e.g. in SKL in handles deep S3 scenerio.
+ * specific to the soc e.g. in SKL in handles deep S3 scenario.
  * Return ACPI_SX values to indicate the previous sleep state.
  */
 int soc_prev_sleep_state(const struct chipset_power_state *ps,
@@ -206,7 +206,7 @@ const char * const *soc_std_gpe_sts_array(size_t *a);
 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);
 
 /*
- * Reads soc specific power management crtitical registers, fills
+ * Reads soc specific power management critical registers, fills
  * chipset_power_state structure variable and prints.
  */
 void soc_fill_power_state(struct chipset_power_state *ps);

src/soc/intel/common/block/include/intelblocks/systemagent.h

@@ -52,10 +52,10 @@ struct sa_mmio_descriptor {
 	const char *description;
 };
 
-/* API to set Fixed MMIO addresss into PCI configuration space */
+/* API to set Fixed MMIO address into PCI configuration space */
 void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
 		size_t count);
-/* API to set Fixed MMIO addresss into MCH base address */
+/* API to set Fixed MMIO address into MCH base address */
 void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,
 		size_t count);
 /*
@@ -69,7 +69,7 @@ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt,
  * SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h
  */
 void enable_bios_reset_cpl(void);
-/* API to enable PAM regisers */
+/* API to enable PAM registers */
 void enable_pam_region(void);
 /* API to enable Power Aware Interrupt Routing through MCHBAR */
 void enable_power_aware_intr(void);

src/soc/intel/common/block/pcr/pcr.c

@@ -59,7 +59,7 @@ static inline void check_pcr_offset_align(uint16_t offset, size_t size)
 
 uint32_t pcr_read32(uint8_t pid, uint16_t offset)
 {
-	/* Ensure the PCR offset is corretcly aligned. */
+	/* Ensure the PCR offset is correctly aligned. */
 	assert(IS_ALIGNED(offset, sizeof(uint32_t)));
 
 	return read32(__pcr_reg_address(pid, offset));
@@ -67,7 +67,7 @@ uint32_t pcr_read32(uint8_t pid, uint16_t offset)
 
 uint16_t pcr_read16(uint8_t pid, uint16_t offset)
 {
-	/* Ensure the PCR offset is corretcly aligned. */
+	/* Ensure the PCR offset is correctly aligned. */
 	check_pcr_offset_align(offset, sizeof(uint16_t));
 
 	return read16(__pcr_reg_address(pid, offset));
@@ -75,7 +75,7 @@ uint16_t pcr_read16(uint8_t pid, uint16_t offset)
 
 uint8_t pcr_read8(uint8_t pid, uint16_t offset)
 {
-	/* Ensure the PCR offset is corretcly aligned. */
+	/* Ensure the PCR offset is correctly aligned. */
 	check_pcr_offset_align(offset, sizeof(uint8_t));
 
 	return read8(__pcr_reg_address(pid, offset));
@@ -94,7 +94,7 @@ static inline void write_completion(uint8_t pid, uint16_t offset)
 
 void pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata)
 {
-	/* Ensure the PCR offset is corretcly aligned. */
+	/* Ensure the PCR offset is correctly aligned. */
 	assert(IS_ALIGNED(offset, sizeof(indata)));
 
 	write32(__pcr_reg_address(pid, offset), indata);
@@ -104,7 +104,7 @@ void pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata)
 
 void pcr_write16(uint8_t pid, uint16_t offset, uint16_t indata)
 {
-	/* Ensure the PCR offset is corretcly aligned. */
+	/* Ensure the PCR offset is correctly aligned. */
 	check_pcr_offset_align(offset, sizeof(uint16_t));
 
 	write16(__pcr_reg_address(pid, offset), indata);
@@ -114,7 +114,7 @@ void pcr_write16(uint8_t pid, uint16_t offset, uint16_t indata)
 
 void pcr_write8(uint8_t pid, uint16_t offset, uint8_t indata)
 {
-	/* Ensure the PCR offset is corretcly aligned. */
+	/* Ensure the PCR offset is correctly aligned. */
 	check_pcr_offset_align(offset, sizeof(uint8_t));
 
 	write8(__pcr_reg_address(pid, offset), indata);

src/soc/intel/common/block/pmc/pmclib.c

@@ -360,7 +360,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
 
 /*
  * Returns prev_sleep_state and also prints all power management registers.
- * Calls soc_prev_sleep_state which may be impelmented by SOC.
+ * Calls soc_prev_sleep_state which may be implemented by SOC.
  */
 static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
 {

src/soc/intel/common/block/sgx/Kconfig

@@ -3,5 +3,5 @@ config SOC_INTEL_COMMON_BLOCK_SGX
 	default n
 	help
 	 Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
-	 instructions that can be used by applications to set aside privat
+	 instructions that can be used by applications to set aside private
 	 regions of code and data.

src/soc/intel/common/block/sgx/sgx.c

@@ -193,11 +193,11 @@ static int is_prmrr_approved(void)
 	msr_t msr;
 	msr = rdmsr(PRMRR_PHYS_MASK_MSR);
 	if (msr.lo & PRMRR_PHYS_MASK_VALID) {
-		printk(BIOS_INFO, "SGX: MCHECK aprroved SGX PRMRR\n");
+		printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");
 		return 1;
 	}
 
-	printk(BIOS_INFO, "SGX: MCHECK did not aprrove SGX PRMRR\n");
+	printk(BIOS_INFO, "SGX: MCHECK did not approve SGX PRMRR\n");
 	return 0;
 }
 
@@ -226,7 +226,7 @@ void sgx_configure(void)
 	/* Lock the SGX feature */
 	lock_sgx();
 
-	/* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */
+	/* Activate the SGX feature, if PRMRR config was approved by MCHECK */
 	if (is_prmrr_approved())
 		activate_sgx();
 }

src/soc/intel/common/block/systemagent/systemagent_def.h

@@ -19,7 +19,7 @@
 
 /* Device 0:0.0 PCI configuration space */
 
-/* GMCH Graphics Comntrol Register */
+/* GMCH Graphics Control Register */
 #define GGC		0x50
 #define  G_GMS_OFFSET	0x8
 #define  G_GMS_MASK	0xff00

src/soc/intel/common/block/uart/uart.c

@@ -106,7 +106,7 @@ bool uart_is_debug_controller(struct device *dev)
 static bool uart_controller_needs_init(struct device *dev)
 {
 	/*
-	 * If coreboot has CONSOLE_SERIAL enabled, the skip re-initalizing
+	 * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
 	 * controller here.
 	 */
 	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))

src/soc/intel/denverton_ns/bootblock/uart.c

@@ -185,7 +185,7 @@ void early_uart_init(void)
 {
 	register int i;
 
-	/* Check: do we have enought elements to init. ? */
+	/* Check: do we have enough elements to init. ? */
 	BUILD_BUG_ON(DENVERTON_UARTS_TO_INI > ELEM_OF_UART_TAB);
 
 	/* HSUART(B0:D26:0-1) GPIO init. */

src/soc/intel/denverton_ns/csme_ie_kt.c

@@ -38,7 +38,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany)
 		struct resource *resource;
 		resource = pci_get_resource(dev, index);
 		/**
-		* Workarond for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
+		* Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE,
 		*  Rev B0 for CSME only)
 		*  CSME&IEs KT IO bar must be 16-byte aligned
 		*/
@@ -59,7 +59,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany)
 static void pci_csme_ie_kt_read_resources(device_t dev)
 {
 	/**
-	* CSME/IE KT has 2 BARs to chec:
+	* CSME/IE KT has 2 BARs to check:
 	*   0x10 - KT IO BAR
 	*   0x14 - KT Memory BAR
 	* CSME/IE KT has no Expansion ROM BAR to check:

src/soc/intel/denverton_ns/gpio.c

@@ -284,7 +284,7 @@ void gpio_configure_pads(const struct pad_config *gpio, size_t num)
 			    (GPIO_CONF_INT_ROUTE_BIT_POS + 1))
 			   << N_PCH_GPIO_RX_NMI_ROUTE);
 
-		// If CFIO is not Working as GPIO mode, Don't move TxDisabe and
+		// If CFIO is not Working as GPIO mode, Don't move TxDisable and
 		// RxDisable
 		if (GpioData->GpioConfig.PadMode == GpioPadModeGpio) {
 			//

src/soc/intel/denverton_ns/include/soc/bootblock.h

@@ -16,13 +16,13 @@
 #ifndef _SOC_DENVERTON_NS_BOOTBLOCK_H_
 #define _SOC_DENVERTON_NS_BOOTBLOCK_H_
 
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
 //void bootblock_cpu_init(void);
 //void bootblock_pch_early_init(void);
 //void bootblock_systemagent_early_init(void);
 void early_uart_init(void);
 
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
 //void enable_smbus(void);
 //void i2c_early_init(void);
 //void pch_early_init(void);

src/soc/intel/denverton_ns/include/soc/gpio_defs.h

@@ -141,7 +141,7 @@
 #define V_PCH_GPIO_RX_PAD_STATE_RAW 0x00
 #define V_PCH_GPIO_RX_PAD_STATE_INT 0x01
 
-// RX Raw Overrride to 1
+// RX Raw Override to 1
 #define B_PCH_GPIO_RX_RAW1 (1 << 28)
 #define N_PCH_GPIO_RX_RAW1 28
 #define V_PCH_GPIO_RX_RAW1_DIS 0x00

src/soc/intel/denverton_ns/include/soc/smm.h

@@ -47,7 +47,7 @@ enum {
 };
 
 /* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
+ * 0 on success, < 0 on failure. */
 int smm_subregion(int sub, void **start, size_t *size);
 
 #if !defined(__PRE_RAM__) && !defined(__SMM___)

src/soc/intel/denverton_ns/lpc.c

@@ -39,7 +39,7 @@
 #define PCH_LP_REDIR_ETR 120
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */

src/soc/intel/skylake/include/soc/bootblock.h

@@ -24,12 +24,12 @@
 static inline void bootblock_fsp_temp_ram_init(void) {}
 #endif
 
-/* Bootblock pre console init programing */
+/* Bootblock pre console init programming */
 void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 void pch_uart_init(void);
 
-/* Bootblock post console init programing */
+/* Bootblock post console init programming */
 void i2c_early_init(void);
 void pch_early_init(void);
 void pch_early_iorange_init(void);

src/soc/intel/skylake/include/soc/vr_config.h

@@ -33,7 +33,7 @@ struct vr_config {
 	 */
 	int vr_config_enable;
 
-	/* Power State X current cuttof in 1/4 Amp increments
+	/* Power State X current cutoff in 1/4 Amp increments
 	 * Range is 0-128A
 	 */
 	int psi1threshold;

src/soc/intel/skylake/irq.c

@@ -233,7 +233,7 @@ void soc_irq_settings(FSP_SIL_UPD *params)
 		sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
 
 	params->NumOfDevIntConfig = intdeventry;
-	/* PxRC to IRQ programing */
+	/* PxRC to IRQ programming */
 	for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) {
 		switch (i) {
 		case PCH_PARC:

src/soc/intel/skylake/memmap.c

@@ -122,7 +122,7 @@ static size_t get_tracehub_size(uintptr_t dram_base,
 
 	/* GDXC MOT */
 	tracehub_base -= GDXC_MOT_MEMORY_SIZE;
-	/* Round down to natual boundary accroding to PSMI size */
+	/* Round down to natural boundary according to PSMI size */
 	tracehub_base = ALIGN_DOWN(tracehub_base, PSMI_BUFFER_AREA_SIZE);
 	/* GDXC IOT */
 	tracehub_base -= GDXC_IOT_MEMORY_SIZE;

src/soc/intel/skylake/romstage/systemagent.c

@@ -34,12 +34,12 @@ void systemagent_early_init(void)
 		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
 	};
 
-	/* Set Fixed MMIO addresss into PCI configuration space */
+	/* Set Fixed MMIO address into PCI configuration space */
 	sa_set_pci_bar(soc_fixed_pci_resources,
 			ARRAY_SIZE(soc_fixed_pci_resources));
-	/* Set Fixed MMIO addresss into MCH base address */
+	/* Set Fixed MMIO address into MCH base address */
 	sa_set_mch_bar(soc_fixed_mch_resources,
 			ARRAY_SIZE(soc_fixed_mch_resources));
-	/* Enable PAM regisers */
+	/* Enable PAM registers */
 	enable_pam_region();
 }

src/soc/intel/skylake/systemagent.c

@@ -28,7 +28,7 @@
 /*
  * SoC implementation
  *
- * Add all known fixed memory ranges for Host Controller/Mmeory
+ * Add all known fixed memory ranges for Host Controller/Memory
  * controller.
  */
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)

src/soc/marvell/mvmap2315/pmic.c

@@ -92,12 +92,12 @@ void ap_start(void *entry)
 
 void no_boot(void)
 {
-	/*TODO: impelement no_boot */
+	/*TODO: implement no_boot */
 }
 
 void charging_screen(void)
 {
-	/*TODO: impelement charging_screen */
+	/*TODO: implement charging_screen */
 }
 
 void full_boot(void)

src/soc/nvidia/tegra210/romstage.c

@@ -60,7 +60,7 @@ void romstage(void)
 	 * Trust Zone needs to be initialized after the DRAM initialization
 	 * because carveout registers are programmed during DRAM init.
 	 * cbmem_initialize() is dependent on the Trust Zone region
-	 * initalization because CBMEM lives right below the Trust Zone which
+	 * initialization because CBMEM lives right below the Trust Zone which
 	 * needs to be properly identified.
 	 */
 	trustzone_region_init();

src/soc/qualcomm/ipq40xx/blobs_init.c

@@ -108,7 +108,7 @@ int initialize_dram(void)
 		die("Fail to Initialize DDR\n");
 
 	/*
-	 * Once DDR initializer finished, its verison can be found at a fixed
+	 * Once DDR initializer finished, its version can be found at a fixed
 	 * address in SRAM.
 	 */
 	printk(BIOS_INFO, "DDR version %.*s initialized\n",

src/soc/qualcomm/ipq806x/blobs_init.c

@@ -80,7 +80,7 @@ int initialize_dram(void)
 		die("Fail to Initialize DDR\n");
 
 	/*
-	 * Once DDR initializer finished, its verison can be found at a fixed
+	 * Once DDR initializer finished, its version can be found at a fixed
 	 * address in SRAM.
 	 */
 	printk(BIOS_INFO, "DDR version %.*s initialized\n",