GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

usbdebug: Drop printk within console_init() 

In case with EARLY_CONSOLE, this printk is called before any other
console is configured to transmit data. This outputs garbage on
CONSOLE_SERIAL as baudrate is not yet programmed.

For case without EARLY_CONSOLE, the order in which different console
drivers initialize is obscure. Might sometimes work properly.

Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3384
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Kyösti Mälkki 2013-06-06 12:53:03 +03:00 committed by Ronald G. Minnich
parent 1b7fd08ca1
commit 5272a5feb7
4 changed files with 0 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/southbridge/intel/bd82x6x/usb_debug.c
View File

@ -38,7 +38,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */ /* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30); dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);

1
src/southbridge/intel/i82801gx/usb_debug.c
View File

@ -45,7 +45,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */ /* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30); dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);

1
src/southbridge/intel/lynxpoint/usb_debug.c
View File

@ -42,7 +42,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */ /* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30); dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);

1
src/southbridge/intel/sch/usb_debug.c
View File

@ -41,7 +41,6 @@ void enable_usbdebug(unsigned int port)
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */ /* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30); dbgctl |= (1 << 30);
write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);