mb/google/dedede: Export EC_IN_RW GPIO to payload

Set up EC_IN_RW GPIO in coreboot.

BUG=b:180686277
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Ic41012d3d4843dcab0f6dd9c28396cb9d5c49f08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

src/mainboard/google/dedede/chromeos.c

@@ -12,6 +12,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
 		{-1, ACTIVE_HIGH, 0, "power"},
 		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
 	};
 	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }

src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h

@@ -17,6 +17,9 @@
 /* EC sync irq is GPP_C15_IRQ */
 #define EC_SYNC_IRQ	GPP_C15_IRQ
 
+/* EC in RW */
+#define GPIO_EC_IN_RW		GPP_C14
+
 /* Memory configuration board straps */
 #define GPIO_MEM_CONFIG_0	GPP_C0
 #define GPIO_MEM_CONFIG_1	GPP_C3