soc/amd/common/acpi/cpu_power_state: introduce and use get_pstate_0_reg

On the Zen-based CPUs, P state 0 corresponds to the first P state MSR,
but on Stoneyridge this isn't the case. Introduce get_pstate_0_reg that
returns 0 for all non-CAR AMD CPUs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icc11e5b6099d37edb934e66fe329d8013d25f68d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/common/block/acpi/cpu_power_state.c

@@ -59,13 +59,14 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
 {
 	union pstate_msr pstate_reg;
 	size_t pstate_count, pstate;
-	uint32_t max_pstate;
+	uint32_t pstate_0_reg, max_pstate;
 
 	pstate_count = 0;
+	pstate_0_reg = get_pstate_0_reg();
 	max_pstate = get_visible_pstate_count();
 
 	for (pstate = 0; pstate <= max_pstate; pstate++) {
-		pstate_reg.raw = rdmsr(PSTATE_MSR(pstate)).raw;
+		pstate_reg.raw = rdmsr(PSTATE_MSR(pstate_0_reg + pstate)).raw;
 
 		if (!pstate_reg.pstate_en)
 			continue;

src/soc/amd/common/block/cpu/noncar/cpu.c

@@ -7,6 +7,11 @@
 #include <smbios.h>
 #include <soc/iomap.h>
 
+uint32_t get_pstate_0_reg(void)
+{
+	return 0;
+}
+
 unsigned int smbios_processor_family(struct cpuid_result res)
 {
 	return 0x6b; /* Zen */

src/soc/amd/common/block/include/amdblocks/cpu.h

@@ -17,6 +17,7 @@ void write_resume_eip(void);
 union pstate_msr; /* proper definition is in soc/msr.h */
 
 uint32_t get_uvolts_from_vid(uint16_t core_vid);
+uint32_t get_pstate_0_reg(void);
 uint32_t get_pstate_core_freq(union pstate_msr pstate_reg);
 uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg);
 const acpi_cstate_t *get_cstate_config_data(size_t *size);