AMD boards: Fix romstage main() declaration

Boards incorrectly used intel include file for AMD board.

Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/include/cpu/amd/car.h

@@ -1,6 +1,8 @@
 #ifndef _CPU_AMD_CAR_H
 #define _CPU_AMD_CAR_H
 
+void main(unsigned long bist);
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 void done_cache_as_ram_main(void);
 void post_cache_as_ram(void);

src/mainboard/aaeon/pfm-540i_revb/romstage.c

@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -49,7 +50,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/amd/db800/romstage.c

@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -44,7 +45,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/amd/norwich/romstage.c

@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -40,7 +41,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/amd/rumba/romstage.c

@@ -20,6 +20,7 @@
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/gx2def.h>
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
@@ -43,7 +44,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/geode_gx2/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {

src/mainboard/artecgroup/dbe61/romstage.c

@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include "spd_table.h"
@@ -52,7 +53,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/bachmann/ot200/romstage.c

@@ -24,6 +24,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
@@ -41,7 +42,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/bcom/winnetp680/romstage.c

@@ -23,6 +23,7 @@
 #include <console/console.h>
 #include <northbridge/via/cn700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include <lib.h>
 #include <spd.h>
@@ -75,7 +76,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -6,6 +6,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/car.h>
 #include <southbridge/amd/cs5536/cs5536.h>
@@ -29,7 +30,6 @@ int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -44,7 +45,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/iei/pm-lx-800-r11/romstage.c

@@ -23,6 +23,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <southbridge/amd/cs5536/early_smbus.c>
@@ -48,7 +49,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include <cpu/amd/geode_lx/syspreinit.c>
 #include <cpu/amd/geode_lx/msrinit.c>
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/iei/pm-lx2-800-r10/romstage.c

@@ -24,6 +24,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <southbridge/amd/cs5536/early_smbus.c>
@@ -48,7 +49,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include <cpu/amd/geode_lx/syspreinit.c>
 #include <cpu/amd/geode_lx/msrinit.c>
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/jetway/j7f2/romstage.c

@@ -23,6 +23,7 @@
 #include <console/console.h>
 #include <northbridge/via/cn700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include <superio/fintek/common/fintek.h>
@@ -80,7 +81,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */

src/mainboard/lippert/frontrunner/romstage.c

@@ -8,6 +8,7 @@
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/gx2def.h>
 #include <southbridge/amd/cs5535/cs5535.h>
 #include "southbridge/amd/cs5535/early_smbus.c"
@@ -69,7 +70,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_gx2/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {

src/mainboard/lippert/hurricane-lx/romstage.c

@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -105,7 +106,6 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/lippert/literunner-lx/romstage.c

@@ -26,6 +26,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
@@ -145,7 +146,6 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int err;

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -25,6 +25,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -80,7 +81,6 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -26,6 +26,7 @@
 #include <console/console.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
@@ -143,7 +144,6 @@ static void mb_gpio_init(void)
 	}
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int err;

src/mainboard/pcengines/alix1c/romstage.c

@@ -23,6 +23,7 @@
 #include <lib.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/car.h>
 #include <southbridge/amd/cs5536/cs5536.h>
@@ -98,7 +99,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/pcengines/alix2d/romstage.c

@@ -23,6 +23,7 @@
 #include <lib.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/car.h>
 #include <southbridge/amd/cs5536/cs5536.h>
@@ -121,7 +122,6 @@ static void mb_gpio_init(void)
 	outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE);       /* Led 3 disabled */
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/traverse/geos/romstage.c

@@ -23,6 +23,7 @@
 #include <lib.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -41,7 +42,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {

src/mainboard/via/epia-cn/romstage.c

@@ -24,6 +24,7 @@
 #include <lib.h>
 #include <northbridge/via/cn700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "southbridge/via/vt8237r/early_serial.c"
@@ -73,7 +74,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 },
 };
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */

src/mainboard/via/epia-m700/romstage.c

@@ -30,6 +30,7 @@
 #include <lib.h>
 #include <northbridge/via/vx800/vx800.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include <string.h>
 /* This file contains the board-special SI value for raminit.c. */
@@ -365,7 +366,6 @@ static void EmbedComInit(void)
 #endif
 
 /* cache_as_ram.inc jumps to here. */
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u16 boot_mode;

src/mainboard/via/epia-m850/romstage.c

@@ -26,6 +26,7 @@
 #include <console/console.h>
 #include <lib.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <string.h>
 #include <timestamp.h>
 
@@ -37,7 +38,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
 
 /* cache_as_ram.inc jumps to here. */
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 tolm;

src/mainboard/via/pc2500e/romstage.c

@@ -24,6 +24,7 @@
 #include <lib.h>
 #include <northbridge/via/cn700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include <superio/ite/common/ite.h>
@@ -49,7 +50,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */
 };
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Enable multifunction for northbridge. */

src/mainboard/via/vt8454c/romstage.c

@@ -23,6 +23,7 @@
 #include <lib.h>
 #include <northbridge/via/cx700/raminit.h>
 #include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
 #include <delay.h>
 #include "northbridge/via/cx700/early_smbus.c"
 #include "lib/debug.c"
@@ -76,7 +77,6 @@ static void enable_shadow_ram(const struct mem_controller *ctrl)
 	pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
 }
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Set statically so it should work with cx700 as well */

src/mainboard/winent/pl6064/romstage.c

@@ -24,6 +24,7 @@
 #include <lib.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/lxdef.h>
 #include <southbridge/amd/cs5536/cs5536.h>
 #include <spd.h>
@@ -46,7 +47,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_lx/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 

src/mainboard/wyse/s50/romstage.c

@@ -22,6 +22,7 @@
 #include <lib.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
 #include <cpu/amd/gx2def.h>
 #include <spd.h>
 #include "southbridge/amd/cs5536/early_smbus.c"
@@ -43,7 +44,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/geode_gx2/syspreinit.c"
 #include "cpu/amd/geode_lx/msrinit.c"
 
-#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl [] = {