sb/intel/x/smbus.c: Correct register access width

The register is 16 bits wide.

Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-03-30 21:18:30 +02:00 committed by Patrick Georgi
parent 544d7e2b91
commit 527b68219f
3 changed files with 3 additions and 14 deletions

View File

@ -14,13 +14,9 @@
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
/* Enable clock gating */
/* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
reg16 = pci_read_config32(dev, 0x80);
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
pci_write_config32(dev, 0x80, reg16);
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);

View File

@ -14,12 +14,9 @@
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
/* Enable clock gating */
reg16 = pci_read_config32(dev, 0x80);
reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14));
pci_write_config32(dev, 0x80, reg16);
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);

View File

@ -13,13 +13,9 @@
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
u16 reg16;
/* Enable clock gating */
/* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
reg16 = pci_read_config32(dev, 0x80);
reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14));
pci_write_config32(dev, 0x80, reg16);
pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);