sb/intel/x/smbus.c: Correct register access width
The register is 16 bits wide. Change-Id: I58d44a17613965e0a27aab5246dcdce68e1a8201 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -14,13 +14,9 @@
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static void pch_smbus_init(struct device *dev)
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{
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struct resource *res;
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u16 reg16;
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/* Enable clock gating */
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/* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
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reg16 = pci_read_config32(dev, 0x80);
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reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
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pci_write_config32(dev, 0x80, reg16);
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pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
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/* Set Receive Slave Address */
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res = find_resource(dev, PCI_BASE_ADDRESS_4);
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@ -14,12 +14,9 @@
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static void pch_smbus_init(struct device *dev)
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{
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struct resource *res;
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u16 reg16;
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/* Enable clock gating */
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reg16 = pci_read_config32(dev, 0x80);
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reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14));
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pci_write_config32(dev, 0x80, reg16);
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pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
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/* Set Receive Slave Address */
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res = find_resource(dev, PCI_BASE_ADDRESS_4);
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@ -13,13 +13,9 @@
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static void pch_smbus_init(struct device *dev)
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{
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struct resource *res;
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u16 reg16;
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/* Enable clock gating */
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/* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
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reg16 = pci_read_config32(dev, 0x80);
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reg16 &= ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14));
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pci_write_config32(dev, 0x80, reg16);
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pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14)));
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/* Set Receive Slave Address */
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res = find_resource(dev, PCI_BASE_ADDRESS_4);
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