Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-46
Creator: Ronald G. Minnich <rminnich@lanl.gov> sc520 fails after NOP git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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arch import user (historical)
parent
c9e2af9ce6
commit
52871c4ad5
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@ -256,7 +256,11 @@ void udelay(int microseconds) {
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int nextbank(int bank)
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{
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int rows,banks, i, ending_adr;
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int rows,banks, cols, i, ending_adr;
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/* this is really ugly, it is right from assembly code.
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* we need to clean it up later
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*/
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start:
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/* write col 11 wrap adr */
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@ -264,45 +268,54 @@ start:
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if(COL11_ADR!=COL11_DATA)
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goto bad_ram;
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print_err("11\n");
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/* write col 10 wrap adr */
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COL10_ADR=COL10_DATA;
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if(COL10_ADR!=COL10_DATA)
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goto bad_ram;
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print_err("10\n");
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/* write col 9 wrap adr */
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COL09_ADR=COL09_DATA;
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if(COL09_ADR!=COL09_DATA)
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goto bad_ram;
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print_err("9\n");
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/* write col 8 wrap adr */
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COL08_ADR=COL08_DATA;
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if(COL08_ADR!=COL08_DATA)
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goto bad_ram;
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print_err("8\n");
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/* write row 14 wrap adr */
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ROW14_ADR=ROW14_DATA;
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if(ROW14_ADR!=ROW14_DATA)
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goto bad_ram;
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print_err("14\n");
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/* write row 13 wrap adr */
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ROW13_ADR=ROW13_DATA;
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if(ROW13_ADR!=ROW13_DATA)
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goto bad_ram;
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print_err("13\n");
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/* write row 12 wrap adr */
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ROW12_ADR=ROW12_DATA;
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if(ROW12_ADR!=ROW12_DATA)
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goto bad_ram;
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print_err("12\n");
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/* write row 11 wrap adr */
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ROW11_ADR=ROW11_DATA;
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if(ROW11_ADR!=ROW11_DATA)
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goto bad_ram;
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print_err("11\n");
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/* write row 10 wrap adr */
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ROW10_ADR=ROW10_DATA;
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if(ROW10_ADR!=ROW10_DATA)
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goto bad_ram;
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print_err("10\n");
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/*
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* read data @ row 12 wrap adr to determine # banks,
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@ -315,6 +328,7 @@ start:
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banks=2;
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if (ROW12_ADR != ROW10_DATA) {
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banks=4;
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print_err("4b\n");
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if(ROW12_ADR != ROW11_DATA) {
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if(ROW12_ADR != ROW12_DATA)
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goto bad_ram;
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@ -322,35 +336,47 @@ start:
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}
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/* validate row mask */
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i=ROW14_ADR;
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if (i<ROW11_DATA)
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rows=ROW14_ADR;
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if (rows<ROW11_DATA)
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goto bad_ram;
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if (i>ROW14_DATA)
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if (rows>ROW14_DATA)
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goto bad_ram;
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/* verify all 4 bytes of dword same */
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if(i&0xffff!=(i>>16)&0xffff)
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if(rows&0xffff!=(rows>>16)&0xffff)
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goto bad_ram;
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if(i&0xff!=(i>>8)&0xff)
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if(rows&0xff!=(rows>>8)&0xff)
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goto bad_ram;
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print_err("rows"); print_err_hex32(rows); print_err("\n");
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/* validate column data */
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i=COL11_ADR;
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if(i<COL08_DATA)
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cols=COL11_ADR;
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if(cols<COL08_DATA)
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goto bad_ram;
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if (i>COL11_DATA)
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if (cols>COL11_DATA)
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goto bad_ram;
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/* verify all 4 bytes of dword same */
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if(i&0xffff!=(i>>16)&0xffff)
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if(cols&0xffff!=(cols>>16)&0xffff)
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goto bad_ram;
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if(i&0xff!=(i>>8)&0xff)
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if(cols&0xff!=(cols>>8)&0xff)
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goto bad_ram;
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print_err("cols"); print_err_hex32(cols); print_err("\n");
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cols -= COL08_DATA;
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i = cols + rows;
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/* wacky end addr calculation */
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/*
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al = 3;
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al -= (i & 0xff);k
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*/
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if(banks==4)
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i+=8; /* <-- i holds merged value */
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/* fix ending addr mask*/
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/*FIXME*/
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/* let's just go with this to start ... see if we can get ANYWHERE */
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ending_adr=0xff;
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bad_reint:
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@ -359,10 +385,12 @@ bad_reint:
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dummy_write();
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/* update ending address register */
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#warning FIX ME NOW I AM BUSTED
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// *(DRCBENDADR+0)=ending_adr;
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DRCBENDADR=ending_adr;
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/* update config register */
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DRCCFG = (banks = 4 ? 8 : 0) | cols & 3;
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/* skip the rest for now */
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bank = 0;
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// DRCCFG=DRCCFG&YYY|ZZZZ;
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if(bank!=0) {
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@ -391,7 +419,7 @@ int sizemem(void)
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DRCTMCTL=0x1e; /* Set SDRAM timing for slowest speed. */
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/* setup loop to do 4 external banks starting with bank 3 */
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print_err("sizemem\n");
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/* enable last bank and setup ending address
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* register for max ram in last bank
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*/
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@ -411,28 +439,35 @@ int sizemem(void)
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/* dummy write for NOP to take effect */
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dummy_write();
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print_err("NOP\n");
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/* 100? 200? */
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udelay(100);
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/* issue all banks precharge */
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DRCCTL=0x02;
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dummy_write();
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print_err("PRE\n");
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/* issue 2 auto refreshes to all banks */
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DRCCTL=0x04;
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dummy_write();
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print_err("AUTO1\n");
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dummy_write();
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print_err("AUTO2\n");
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/* issue LOAD MODE REGISTER command */
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DRCCTL=0x03;
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dummy_write();
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print_err("LOAD MODE REG\n");
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DRCCTL=0x04;
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for (i=0; i<8; i++) /* refresh 8 times */
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dummy_write();
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print_err("8 dummy writes\n");
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/* set control register to NORMAL mode */
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DRCCTL=0x00;
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print_err("normal\n");
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nextbank(3);
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@ -64,10 +64,14 @@ static void main(unsigned long bist)
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setupsc520();
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uart_init();
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console_init();
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// while(1)
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print_err("HI THERE!\r\n");
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sizemem();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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// report_bist_failure(bist);
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#if 0
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