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amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values 

The existing MCT code did not properly set up the On Die Termination
(ODT) or timing values for registered DIMMs.  Use the BKDG recommended
values when registered DIMMs are installed.

Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12005
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Timothy Pearson 2015-06-25 17:07:57 -05:00 committed by Stefan Reinauer
parent 38508a0ff1
commit 5288cedac1
1 changed files with 290 additions and 132 deletions
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162
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -828,13 +828,97 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
if (package_type == PT_GR) {
/* Socket G34 */
if (pDCTstat->Status & (1 << SB_Registered)) {
/* RDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */
if (MaxDimmsInstallable == 1) {
rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
if (MemClkFreq == 0x4) {
/* DDR3-667 */
calibration_code = 0x00112222;
} else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x10112222;
} else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x20112222;
} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
/* DDR3-1333 - DDR3-1600 */
calibration_code = 0x30112222;
} else if (MemClkFreq == 0x16) {
/* DDR3-1866 */
calibration_code = 0x30332222;
}
if (rank_count_dimm0 == 4) {
calibration_code &= ~(0xff << 16);
calibration_code |= 0x22 << 16;
}
} else if (MaxDimmsInstallable == 2) {
rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
if (dimm_count == 1) {
/* 1 DIMM detected */
if (MemClkFreq == 0x4) {
/* DDR3-667 */
calibration_code = 0x00112222;
} else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x10112222;
} else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x20112222;
} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
/* DDR3-1333 - DDR3-1600 */
calibration_code = 0x30112222;
}
if ((rank_count_dimm0 == 4) || (rank_count_dimm1 == 4)) {
calibration_code &= ~(0xff << 16);
calibration_code |= 0x22 << 16;
}
} else if (dimm_count == 2) {
/* 2 DIMMs detected */
rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0];
rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
if (MemClkFreq == 0x4) {
/* DDR3-667 */
calibration_code = 0x10222222;
} else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x20222222;
} else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x30222222;
} else if (MemClkFreq == 0xe) {
/* DDR3-1333 */
calibration_code = 0x30222222;
} else if (MemClkFreq == 0x12) {
/* DDR3-1600 */
calibration_code = 0x30222222;
}
}
} else if (MaxDimmsInstallable == 3) {
/* TODO
* 3 DIMM/channel support unimplemented
*/
}
} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
/* LRDIMM */
/* TODO
* LRDIMM support unimplemented
*/
} else {
/* UDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
if (MaxDimmsInstallable == 1) {
if (MemClkFreq == 0x4) {
/* DDR3-667 */
calibration_code = 0x00112222;
}
else if (MemClkFreq == 0x6) {
} else if (MemClkFreq == 0x6) {
/* DDR3-800 */
calibration_code = 0x10112222;
} else if (MemClkFreq == 0xa) {
@ -893,6 +977,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
* 3 DIMM/channel support unimplemented
*/
}
}
} else {
/* TODO
* Other socket support unimplemented
@ -923,6 +1008,67 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
if (package_type == PT_GR) {
/* Socket G34 */
if (pDCTstat->Status & (1 << SB_Registered)) {
/* RDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */
if (MaxDimmsInstallable == 1) {
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
/* DDR3-667 - DDR3-800*/
calibration_code = 0x00000000;
} else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x003c3c3c;
} else if (MemClkFreq == 0xe) {
/* DDR3-1333 */
calibration_code = 0x003a3a3a;
} else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) {
/* DDR3-1600 - DDR3-1866 */
calibration_code = 0x00393939;
}
} else if (MaxDimmsInstallable == 2) {
if (dimm_count == 1) {
/* 1 DIMM detected */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
/* DDR3-667 - DDR3-800*/
calibration_code = 0x00000000;
} else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x00393c39;
} else if (MemClkFreq == 0xe) {
/* DDR3-1333 */
calibration_code = 0x00373a37;
} else if (MemClkFreq == 0x12) {
/* DDR3-1600 */
calibration_code = 0x00363936;
}
} else if (dimm_count == 2) {
/* 2 DIMMs detected */
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
/* DDR3-667 - DDR3-800*/
calibration_code = 0x00000000;
} else if (MemClkFreq == 0xa) {
/* DDR3-1066 */
calibration_code = 0x003a3c3a;
} else if (MemClkFreq == 0xe) {
/* DDR3-1333 */
calibration_code = 0x00383a38;
} else if (MemClkFreq == 0x12) {
/* DDR3-1600 */
calibration_code = 0x00353935;
}
}
} else if (MaxDimmsInstallable == 3) {
/* TODO
* 3 DIMM/channel support unimplemented
*/
}
} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
/* LRDIMM */
/* TODO
* LRDIMM support unimplemented
*/
} else {
/* UDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
if (MaxDimmsInstallable == 1) {
rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
@ -1013,6 +1159,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
* 3 DIMM/channel support unimplemented
*/
}
}
} else {
/* TODO
* Other socket support unimplemented
@ -1043,6 +1190,16 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
if (package_type == PT_GR) {
/* Socket G34 */
if (pDCTstat->Status & (1 << SB_Registered)) {
/* RDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */
slow_access = 0;
} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
/* LRDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 75 */
slow_access = 0;
} else {
/* UDIMM */
/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
if (MaxDimmsInstallable == 1) {
rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1];
@ -1093,6 +1250,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
* 3 DIMM/channel support unimplemented
*/
}
}
} else {
/* TODO
* Other socket support unimplemented