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soc/tigerlake: Correct FSP log interface 

Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

BUG=None
BRANCH=None
TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-02-28 17:20:05 -08:00 committed by Patrick Georgi
parent 23f870ad3a
commit 528ae9e811
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
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@ -61,7 +61,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* UART Debug Log */ /* UART Debug Log */
m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB :
DEBUG_INTERFACE_SERIAL_IO|DEBUG_INTERFACE_TRACEHUB;
m_cfg->PcdIsaSerialUartBase = 0x0; m_cfg->PcdIsaSerialUartBase = 0x0;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;