Vortex86EX southbridge routes more built-in PCI device IRQs.
Routes IRQs for USB device, SPI1, MOTOR, HD audio, CAN bus. Change-Id: I995a5c6d3ed6a7dca4f0d21545c928132ccbbc21 Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -46,18 +46,31 @@ static const unsigned char irq_to_int_routing[16] = {
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#define RT0_IRQ_SHIFT 0
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/* S/B Extend PCI Interrupt routing table reg(0xb4) field bit shift. */
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#define CAN_IRQ_SHIFT 28
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#define HDA_IRQ_SHIFT 20
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#define USBD_IRQ_SHIFT 16
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#define SIDE_IRQ_SHIFT 12
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#define PIDE_IRQ_SHIFT 8
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/* S/B function 1 Extend PCI Interrupt routing table reg 2(0xb4)
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* field bit shift.
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*/
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#define SPI1_IRQ_SHIFT 8
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#define MOTOR_IRQ_SHIFT 0
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/* in-chip PCI device IRQs(0 for disabled). */
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#define EHCII_IRQ 5
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#define OHCII_IRQ 5
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#define MAC_IRQ 6
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#define USBD_IRQ 0
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#define CAN_IRQ 10
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#define HDA_IRQ 7
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#define USBD_IRQ 6
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#define PIDE_IRQ 5
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#define SPI1_IRQ 10
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#define MOTOR_IRQ 11
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/* RT0-3 IRQs. */
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#define RT3_IRQ 3
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#define RT2_IRQ 4
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@ -179,9 +192,11 @@ static void pci_routing_fixup(struct device *dev)
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int_routing |= irq_to_int_routing[EHCII_IRQ] << EHCIH_IRQ_SHIFT;
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int_routing |= irq_to_int_routing[OHCII_IRQ] << OHCII_IRQ_SHIFT;
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int_routing |= irq_to_int_routing[MAC_IRQ] << MAC_IRQ_SHIFT;
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pci_write_config32(dev, SB_REG_PIRQ_X_ROUT, int_routing);
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pci_write_config32(dev, SB_REG_PIRQ_ROUTE, int_routing);
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/* Setup S/B PCI Extend Interrupt routing table reg(0xb4). */
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ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT;
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ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT;
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ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT;
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#if CONFIG_IDE_NATIVE_MODE
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/* IDE in native mode, only uses one IRQ. */
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@ -192,7 +207,7 @@ static void pci_routing_fixup(struct device *dev)
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ext_int_routing |= irq_to_int_routing[IDE2_LEGACY_IRQ] << SIDE_IRQ_SHIFT;
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ext_int_routing |= irq_to_int_routing[IDE1_LEGACY_IRQ] << PIDE_IRQ_SHIFT;
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#endif
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pci_write_config32(dev, SB_REG_PIRQ_X_ROUT2, ext_int_routing);
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pci_write_config32(dev, SB_REG_EXT_PIRQ_ROUTE, ext_int_routing);
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/* Assign in-chip PCI device IRQs. */
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if (MAC_IRQ) {
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@ -208,6 +223,14 @@ static void pci_routing_fixup(struct device *dev)
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unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 };
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pci_assign_irqs(0, 0xc, irqs);
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}
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if (CAN_IRQ) {
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unsigned char irqs[4] = { CAN_IRQ, 0, 0, 0 };
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pci_assign_irqs(0, 0x11, irqs);
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}
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if (HDA_IRQ) {
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unsigned char irqs[4] = { HDA_IRQ, 0, 0, 0 };
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pci_assign_irqs(0, 0xe, irqs);
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}
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if (USBD_IRQ) {
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unsigned char irqs[4] = { USBD_IRQ, 0, 0, 0 };
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pci_assign_irqs(0, 0xf, irqs);
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@ -514,14 +537,28 @@ static void vortex86_sb_read_resources(device_t dev)
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vortex86_sb_set_spi_flash_size(dev, flash_size);
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}
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static void southbridge_init_func1(struct device *dev)
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{
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/* Handle S/B function 1 PCI IRQ routing. (SPI1/MOTOR) */
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u32 ext_int_routing2 = 0;
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/* Setup S/B function 1 PCI Extend Interrupt routing table reg 2(0xb4). */
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ext_int_routing2 |= irq_to_int_routing[SPI1_IRQ] << SPI1_IRQ_SHIFT;
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ext_int_routing2 |= irq_to_int_routing[MOTOR_IRQ] << MOTOR_IRQ_SHIFT;
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pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2);
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/* Assign in-chip PCI device IRQs. */
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if (SPI1_IRQ || MOTOR_IRQ) {
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unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 };
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pci_assign_irqs(0, 0x10, irqs);
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}
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}
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static void southbridge_init(struct device *dev)
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{
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if (dev->device == 0x6011) {
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/* It is EX CPU southbridge */
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if (get_pci_dev_func(dev) != 0) {
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/* only for function 0, skip function 1 */
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return;
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}
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/* Check it is function 0 or 1. (Same Vendor/Device ID) */
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if (get_pci_dev_func(dev) != 0) {
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southbridge_init_func1(dev);
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return;
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}
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upload_dmp_keyboard_firmware(dev);
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vortex_sb_init(dev);
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@ -23,7 +23,7 @@
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#define SB PCI_DEV(0, 7, 0)
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#define SB_REG_LPCCR 0x41
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#define SB_REG_FRCSCR 0x42
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#define SB_REG_PIRQ_X_ROUT 0x58
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#define SB_REG_PIRQ_ROUTE 0x58
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#define SB_REG_UART_CFG_IO_BASE 0x60
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#define SB_REG_GPIO_CFG_IO_BASE 0x62
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#define SB_REG_CS_BASE0 0x90
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@ -31,12 +31,15 @@
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#define SB_REG_CS_BASE1 0x98
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#define SB_REG_CS_BASE_MASK1 0x9c
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#define SB_REG_IPPCR 0xb0
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#define SB_REG_PIRQ_X_ROUT2 0xb4
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#define SB_REG_EXT_PIRQ_ROUTE 0xb4
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#define SB_REG_OCDCR 0xbc
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#define SB_REG_IPFCR 0xc0
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#define SB_REG_FRWPR 0xc4
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#define SB_REG_STRAP 0xce
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#define SB1 PCI_DEV(0, 7, 1)
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#define SB1_REG_EXT_PIRQ_ROUTE2 0xb4
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#define SYSTEM_CTL_PORT 0x92
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#endif /* SOUTHBRIDGE_H */
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