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soc/intel/skylake: Enable SDXC depending on devicetree configuration 

Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.

All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-07-29 21:44:36 +02:00 committed by Michael Niewöhner
parent 0da148e326
commit 52919523c1
28 changed files with 10 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/51nb/x210/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
@ -144,6 +143,7 @@ chip soc/intel/skylake
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.6 off end # SDXC
device pci 1f.0 on
chip ec/51nb/npce985la0dx
device pnp 0c09.0 on end

4
src/mainboard/asrock/h110m/devicetree.cb
View File

@ -265,9 +265,7 @@ chip soc/intel/skylake
device pci 1e.3 off end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 off # SDCard
register "ScsSdCardEnabled" = "0"
end
device pci 1e.6 off end # SDCard
device pci 1f.0 on # LPC bridge
subsystemid 0x1849 0x1a43

1
src/mainboard/google/eve/devicetree.cb
View File

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -75,7 +75,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/glados/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

2
src/mainboard/google/glados/variants/caroline/overridetree.cb
View File

@ -1,7 +1,5 @@
chip soc/intel/skylake
register "ScsSdCardEnabled" = "2"
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms

2
src/mainboard/google/glados/variants/cave/overridetree.cb
View File

@ -1,7 +1,5 @@
chip soc/intel/skylake
register "ScsSdCardEnabled" = "2"
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms

2
src/mainboard/google/glados/variants/glados/overridetree.cb
View File

@ -1,7 +1,5 @@
chip soc/intel/skylake
register "ScsSdCardEnabled" = "2"
register "PmConfigSlpS4MinAssert" = "1" # 1s
register "PmConfigSlpSusMinAssert" = "1" # 500ms

2
src/mainboard/google/glados/variants/sentry/overridetree.cb
View File

@ -1,7 +1,5 @@
chip soc/intel/skylake
register "ScsSdCardEnabled" = "2"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"

1
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@ -26,7 +26,6 @@ chip soc/intel/skylake
register "HeciEnabled" = "0"
register "IoBufferOwnership" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"
register "PchHdaVcType" = "Vc1"

1
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View File

@ -3,7 +3,6 @@ chip soc/intel/skylake
# FSP Configuration
register "DspEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"

2
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View File

@ -6,7 +6,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PmTimerDisabled" = "0"
register "serirq_mode" = "SERIRQ_CONTINUOUS"
@ -171,6 +170,7 @@ chip soc/intel/skylake
device pci 1e.2 on end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.6 off end # SDXC
device pci 1f.0 on
#chip drivers/pc80/tpm
# device pnp 0c31.0 on end

1
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -27,7 +27,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -21,7 +21,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

2
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -52,7 +52,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
@ -201,6 +200,7 @@ chip soc/intel/skylake
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.2 on end # PCI Express Port 11
device pci 1d.3 on end # PCI Express Port 12
device pci 1e.6 off end # SDXC
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "PmTimerDisabled" = "1"

2
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -57,7 +57,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "0"
@ -192,6 +191,7 @@ chip soc/intel/skylake
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.6 off end # SDXC
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end

2
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
@ -228,6 +227,7 @@ chip soc/intel/skylake
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # Serial IO UART0
device pci 1e.6 off end # SDXC
device pci 1f.0 on # LPC
chip drivers/pc80/tpm
device pnp 0c31.0 on end

2
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@ -8,7 +8,6 @@ chip soc/intel/skylake
# FSP Configuration
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Disabled"
@ -140,6 +139,7 @@ chip soc/intel/skylake
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # SPI #0
device pci 1e.6 off end # SDXC
device pci 1f.0 on # LPC Interface
chip superio/common
device pnp 2e.0 on end

4
src/soc/intel/skylake/chip.c
View File

@ -257,7 +257,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
params->ScsEmmcEnabled = dev ? dev->enabled : 0;
params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
params->ScsSdCardEnabled = config->ScsSdCardEnabled;
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
params->ScsSdCardEnabled = dev && dev->enabled;
if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) {
params->PchScsEmmcHs400DllDataValid =

1
src/soc/intel/skylake/chip.h
View File

@ -306,7 +306,6 @@ struct soc_intel_skylake_config {
/* eMMC and SD */
u8 ScsEmmcHs400Enabled;
u8 ScsSdCardEnabled;
u8 EmmcHs400DllNeed;
u8 ScsEmmcHs400RxStrobeDll1;
u8 ScsEmmcHs400TxDataDll;