soc/intel: Add Raptor Lake device IDs

Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.

References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/cpu/intel/cpu_ids.h

@@ -64,5 +64,6 @@
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
 #define CPUID_RAPTORLAKE_P_J0		0xb06a2
+#define CPUID_RAPTORLAKE_P_Q0		0xb06a3
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -4013,7 +4013,9 @@
 #define PCI_DID_INTEL_RPL_P_GT1				0xa720
 #define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
 #define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
-
+#define PCI_DID_INTEL_RPL_P_GT4				0xa7a9
+#define PCI_DID_INTEL_RPL_P_GT5				0xa7a1
+#define PCI_DID_INTEL_RPL_P_GT6				0xa721
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4136,6 +4138,7 @@
 #define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
+#define PCI_DID_INTEL_RPL_P_ID_3		0xa708
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22

src/soc/intel/alderlake/bootblock/report_platform.c

@@ -35,6 +35,7 @@ static struct {
 	{ CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" },
 	{ CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" },
 	{ CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" },
+	{ CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" },
 };
 
 static struct {
@@ -72,6 +73,8 @@ static struct {
 	{ PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" },
 	{ PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" },
 	{ PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" },
+	{ PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" },
+
 };
 
 static struct {
@@ -196,6 +199,9 @@ static struct {
 	{ PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" },
 	{ PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" },
 	{ PCI_DID_INTEL_RPL_P_GT3, "Raptorlake P GT3" },
+	{ PCI_DID_INTEL_RPL_P_GT4, "Raptorlake P GT4" },
+	{ PCI_DID_INTEL_RPL_P_GT5, "Raptorlake P GT5" },
+	{ PCI_DID_INTEL_RPL_P_GT6, "Raptorlake P GT6" },
 };
 
 static inline uint8_t get_dev_revision(pci_devfn_t dev)

src/soc/intel/alderlake/cpu.c

@@ -243,6 +243,7 @@ enum adl_cpu_type get_adl_cpu_type(void)
 	const uint16_t rpl_p_mch_ids[] = {
 		PCI_DID_INTEL_RPL_P_ID_1,
 		PCI_DID_INTEL_RPL_P_ID_2,
+		PCI_DID_INTEL_RPL_P_ID_3,
 	};
 
 	const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),

src/soc/intel/common/block/cpu/mp_init.c

@@ -82,6 +82,7 @@ static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 },
 	{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 },
 	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0 },
+	{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0 },
 	{ 0, 0 },
 };
 

src/soc/intel/common/block/graphics/graphics.c

@@ -180,6 +180,9 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DID_INTEL_RPL_P_GT1,
 	PCI_DID_INTEL_RPL_P_GT2,
 	PCI_DID_INTEL_RPL_P_GT3,
+	PCI_DID_INTEL_RPL_P_GT4,
+	PCI_DID_INTEL_RPL_P_GT5,
+	PCI_DID_INTEL_RPL_P_GT6,
 	PCI_DID_INTEL_MTL_M_GT2,
 	PCI_DID_INTEL_MTL_P_GT2_1,
 	PCI_DID_INTEL_MTL_P_GT2_2,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -469,6 +469,7 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_ADL_N_ID_4,
 	PCI_DID_INTEL_RPL_P_ID_1,
 	PCI_DID_INTEL_RPL_P_ID_2,
+	PCI_DID_INTEL_RPL_P_ID_3,
 	0
 };