pistachio: implement timer support

C0_COUNT register is a free running counter clocked by the CPU
frequency divided by two. On the FPGA board it results in 25 MHz, on
real SOCs it will have to be figured out later.

Some magic addresses and numbers are used to find out if the code is
running on the FPGA board.

timestamp_get() and timer_monotonic_get() are kept in the same file.

The CPU initialization makes sure that CO COUNT is in fact enabled and
starts from zero.

BRANCH=none
BUG=chrome-os-partner:33595,chrome-os-partner:31438
TEST=with timer enabled, the startup code properly initializes UART
     and prints the coreboot bootblock banner message on the serial
     console.

Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05
Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/227888
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9188
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/imgtec/pistachio/Makefile.inc

@@ -31,16 +31,13 @@ ramstage-y += uart.c
 endif
 
 bootblock-y += monotonic_timer.c
-bootblock-y += timestamp.c
 
 ramstage-y += cbmem.c
 ramstage-y += monotonic_timer.c
-ramstage-y += timestamp.c
 
 romstage-y += cbmem.c
 romstage-y += romstage.c
 romstage-y += monotonic_timer.c
-romstage-y += timestamp.c
 
 CPPFLAGS_common += -Isrc/soc/imgtec/pistachio/include/
 

src/soc/imgtec/pistachio/bootblock.c

@@ -19,6 +19,21 @@
  * MA 02110-1301 USA
  */
 
+#include <stdint.h>
+#include <arch/cpu.h>
+
 static void bootblock_cpu_init(void)
 {
+	uint32_t cause;
+
+	/*
+	 * Make sure the count register is counting by clearing the "Disable
+	 * Counter" bit, in case it is set.
+	 */
+	cause = read_c0_cause();
+	if (cause & C0_CAUSE_DC)
+		write_c0_cause(cause & ~(C0_CAUSE_DC));
+
+	/* And make sure that it starts from zero. */
+	write_c0_count(0);
 }

src/soc/imgtec/pistachio/include/soc/cpu.h

@@ -21,4 +21,11 @@
 #define IMG_SPIM0_BASE_ADDRESS	0xB8100F00
 #define IMG_SPIM1_BASE_ADDRESS	0xB8101000
 
+/*
+ * Reading at this address allows to identify the platform the code is running
+ * on.
+ */
+#define IMG_PLATFORM_ID()	(*((unsigned *)0xB8149060))
+#define IMG_PLATFORM_ID_SILICON 0xF00D0006
+
 #endif

src/soc/imgtec/pistachio/monotonic_timer.c

@@ -17,9 +17,33 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <stdint.h>
 #include <timer.h>
+#include <timestamp.h>
+#include <arch/cpu.h>
+#include <soc/cpu.h>
+
+static int get_count_mhz_freq(void)
+{
+	static unsigned count_mhz_freq;
+
+	if (!count_mhz_freq) {
+		if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
+			count_mhz_freq = 25; /* FPGA board */
+			/*
+			 * Will need some means of finding out the counter
+			 * frequency on a real SOC
+			 */
+	}
+	return count_mhz_freq;
+}
 
 void timer_monotonic_get(struct mono_time *mt)
 {
-	/* to be defined */
+	mt->microseconds = (long)timestamp_get();
+}
+
+uint64_t timestamp_get(void)
+{
+	return read_c0_count()/get_count_mhz_freq();
 }

src/soc/imgtec/pistachio/timestamp.c

@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2014 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <timestamp.h>
-
-uint64_t timestamp_get(void)
-{
-	return 0;
-}