soc/cavium/cn81xx: Fix minor things
* Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -39,16 +39,11 @@ romstage-y += timer.c
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romstage-y += spi.c
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romstage-y += uart.c
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romstage-$(CONFIG_DRIVERS_UART) += uart.c
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romstage-< += cpu.c
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romstage-y += cbmem.c
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romstage-y += sdram.c
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romstage-y += mmu.c
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romstage-y += ../common/cbmem.c
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# BDK coreboot interface
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romstage-y += ../common/bdk-coreboot.c
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################################################################################
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# ramstage
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@ -64,12 +59,10 @@ ramstage-y += soc.c
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ramstage-y += cpu.c
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ramstage-y += cpu_secondary.S
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ramstage-y += ecam0.c
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ramstage-y += cbmem.c
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ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
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# BDK coreboot interface
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ramstage-y += ../common/bdk-coreboot.c
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BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0
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CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
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@ -21,6 +21,7 @@
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void *cbmem_top(void)
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{
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return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
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MAX_DRAM_ADDRESS);
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/* Make sure not to overlap with reserved ATF scratchpad */
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return (void *)min((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB,
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4ULL * GiB);
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}
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@ -309,7 +309,8 @@ void bootmem_platform_add_ranges(void)
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BM_MEM_RESERVED);
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/* Scratchpad for ATF SATA quirks */
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bootmem_add_range(sdram_size_mb() * KiB, 1 * MiB, BM_MEM_RESERVED);
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bootmem_add_range((sdram_size_mb() - 1) * MiB, 1 * MiB,
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BM_MEM_RESERVED);
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}
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static void soc_read_resources(device_t dev)
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@ -22,13 +22,12 @@ bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock.c
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################################################################################
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# romstage
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romstage-y += cbmem.c
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romstage-y += bdk-coreboot.c
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################################################################################
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# ramstage
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ramstage-y += cbmem.c
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ramstage-y += bdk-coreboot.c
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CPPFLAGS_common += -Isrc/soc/cavium/common/include
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