GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/socket_mPGA604: Enable TSC_CONSTANT_RATE 

We can use intel/common implementation for tsc_freq_mhz().

Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-07-06 07:57:20 +03:00
parent fe26be1181
commit 52b1e2814a
2 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/model_f2x/Makefile.inc
View File

@ -1,3 +1,5 @@
subdirs-y += ../common
ramstage-y += model_f2x_init.c ramstage-y += model_f2x_init.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*)

3
src/cpu/intel/socket_mPGA604/Kconfig
View File

@ -9,9 +9,12 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX select MMX
select SSE select SSE
select UDELAY_TSC select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM select SIPI_VECTOR_IN_ROM
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
# mPGA604 are usually Intel Netburst CPUs which should have SSE2 # mPGA604 are usually Intel Netburst CPUs which should have SSE2
# but the ramtest.c code on the Dell S1850 seems to choke on # but the ramtest.c code on the Dell S1850 seems to choke on