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sb/intel/lynxpoint: Add Kconfig option to hide Intel ME 

On lynxpoint devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.

Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Matt DeVillier 2022-12-21 14:47:37 -06:00 committed by Felix Held
parent 42f704a967
commit 52c553e838
2 changed files with 12 additions and 1 deletions
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8
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -84,4 +84,12 @@ config SERIALIO_UART_CONSOLE
config CONSOLE_UART_BASE_ADDRESS
default 0xd6000000 if SERIALIO_UART_CONSOLE
config DISABLE_ME_PCI
bool "Disable Intel ME PCI interface (MEI1)"
default y
help
Disable and hide the ME PCI interface during finalize stage of boot.
This will prevent the OS (and userspace apps) from interacting with
the ME via the PCI interface after boot.
endif

5
src/southbridge/intel/lynxpoint/me.c
View File

@ -543,6 +543,9 @@ void intel_me_finalize(struct device *dev)
/* Try to send EOP command so ME stops accepting other commands */
mkhi_end_of_post();
if (!CONFIG(DISABLE_ME_PCI))
return;
/* Make sure IO is disabled */
pci_and_config16(dev, PCI_COMMAND,
~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
@ -903,7 +906,7 @@ static void intel_me_init(struct device *dev)
static void intel_me_enable(struct device *dev)
{
/* Avoid talking to the device in S3 path */
if (acpi_is_wakeup_s3()) {
if (acpi_is_wakeup_s3() && CONFIG(DISABLE_ME_PCI)) {
dev->enabled = 0;
pch_disable_devfn(dev);
}