From 52f3bd158a2edf92ec163912ee6b4053f976c636 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 17 Jul 2019 17:12:50 -0600 Subject: [PATCH] sb/amd/sb800: Remove bit shift that does nothing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This bit shift attempts to set bits 8 and 9 of the byte variable (counting from 0). However, as the name suggests, this variable is only 8 bits wide, so the shift does nothing. Reading section 7.5 of the AMD SB800-Series Southbridges Register Programming Requirements manual, bits 8 and 9 are already set by default, so we can remove the bit shift. (Alternatively, we could try setting the corresponding bits one byte higher in 0xF1 if needed.) Change-Id: I645236441e02925ee01339378d213cb343027363 Signed-off-by: Jacob Garber Found-by: Coverity CID 1229582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34395 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/amd/sb800/usb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index bc8c1c664e..063750dc46 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -42,7 +42,6 @@ static void usb_init(struct device *dev) /* RPR 7.4 Enable the USB controller to get reset by any software that generate a PCIRst# condition */ byte = pm_ioread(0xF0); byte |= (1 << 2); - byte |= 3 << 8; /* rpr 7.5 */ pm_iowrite(0xF0, byte); /* RPR 7.9 Disable OHCI MSI Capability. */