soc/amd/picasso: Use AMD common SATA driver

This change enables the use of AMD common block SATA driver for
Picasso. Since the common driver provides ACPI device name and PCI
device for SATA in SSDT, these are removed from picasso chip.c and
sb_pci0_fch.asl.

BUG=b:153858769
TEST=Verified that "STCR" device is correctly reported on trembyle in
SSDT.

Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-04-27 15:45:20 -07:00
parent 088b9e337c
commit 52f8926159
3 changed files with 4 additions and 7 deletions

View File

@ -26,6 +26,10 @@ static struct device_operations sata_ops = {
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_CZ_SATA,
PCI_DEVICE_ID_AMD_CZ_SATA_AHCI,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0,
PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER1,
0
};

View File

@ -23,11 +23,6 @@ Method(_OSC,4)
/* Describe the Southbridge devices */
/* 0:11.0 - SATA */
Device(STCR) {
Name(_ADR, 0x00110000)
} /* end STCR */
/* 0:14.0 - SMBUS */
Device(SBUS) {
Name(_ADR, 0x00140000)

View File

@ -65,8 +65,6 @@ const char *soc_acpi_name(const struct device *dev)
return "AZHD";
case LPC_DEVFN:
return "LPCB";
case SATA_DEVFN:
return "STCR";
case SMBUS_DEVFN:
return "SBUS";
case XHCI0_DEVFN: