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soc/intel/alderlake_n: Allow using the microcode repo 

Allow users of Alderlake N processors to use the microcode repository
and also add their related microcode blob to the list of microcodes
which should be included in the coreboot rom.

Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
This commit is contained in:
Felix Singer 2023-06-03 06:12:57 +02:00 committed by Felix Singer
parent b61ee16fb3
commit 52fb64be42
2 changed files with 2 additions and 3 deletions
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1
src/soc/intel/alderlake/Kconfig
View File

@ -111,7 +111,6 @@ config SOC_INTEL_ALDERLAKE_PCH_M
config SOC_INTEL_ALDERLAKE_PCH_N
bool
select SOC_INTEL_ALDERLAKE
select MICROCODE_BLOB_UNDISCLOSED
help
Choose this option if your mainboard has a PCH-N chipset.

4
src/soc/intel/alderlake/Makefile.inc
View File

@ -78,8 +78,9 @@ cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05
# RPL-S/HX B0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01
# 06-b7-00, 06-b7-02, 06-b7-05 RPL-S/HX A0, C0 and H0 missing
else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00
else
ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
# 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples
# Missing 06-9a-02 ADL-P K0
# ADL-P L0, ADL-P R0 and ADL-M R0
@ -87,7 +88,6 @@ cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9a-04
# RPL-P/H J0, RPL-U Q0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-ba-02
endif
endif
ifeq ($(CONFIG_STITCH_ME_BIN),y)