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soc/intel/{tigerlake,alderlake,meteorlake}: Start to unify the TCSS ACPI 

The ACPI used for Tiger Lake, Alder Lake and Meteor Lake are very
similar, so can be moved to shared code.

This commit aligns minor difference between then, such as comments and
tabs/spaces.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If6554c7ef9e83740d7ec5dcca6a9d7e32fb182db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77453
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2023-08-25 13:46:08 +01:00 committed by Felix Held
parent 90e1346d51
commit 53048c2a54
3 changed files with 24 additions and 14 deletions
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14
src/soc/intel/alderlake/acpi/tcss_dma.asl
View File

@ -35,6 +35,10 @@ Method (_S0W, 0x0)
#endif // D3COLD_SUPPORT #endif // D3COLD_SUPPORT
} }
/*
* Get power resources that are dependent on this device for Operating System Power Management
* to put the device in the D0 device state
*/
Method (_PR0) Method (_PR0)
{ {
#if CONFIG(D3COLD_SUPPORT) #if CONFIG(D3COLD_SUPPORT)
@ -49,7 +53,7 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // D3COLD_SUPPORT #endif // D3COLD_SUPPORT
} }
Method (_PR3) Method (_PR3)
@ -74,8 +78,8 @@ Method (_PR3)
*/ */
Method (D3CX, 0, Serialized) Method (D3CX, 0, Serialized)
{ {
DD3E = 0 /* Disable DMA RTD3 */ DD3E = 0x00 /* Disable DMA RTD3 */
STAT = 0x1 STAT = 0x01
} }
/* /*
@ -83,8 +87,8 @@ Method (D3CX, 0, Serialized)
*/ */
Method (D3CE, 0, Serialized) Method (D3CE, 0, Serialized)
{ {
DD3E = 1 /* Enable DMA RTD3 */ DD3E = 0x01 /* Enable DMA RTD3 */
STAT = 0 STAT = 0x00
} }
/* /*

6
src/soc/intel/meteorlake/acpi/tcss.asl
View File

@ -392,7 +392,10 @@ Scope (\_SB.PCI0)
} }
/* From RegBar Base, IOM_TypeC_SW_configuration_1 is at offset 0x40 */ /*
* From RegBar Base, IOM_TypeC_SW_configuration_1 is in offset 0xC10040, where
* 0x40 is the register offset.
*/
OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100) OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100)
Field (IOMR, DWordAcc, NoLock, Preserve) Field (IOMR, DWordAcc, NoLock, Preserve)
{ {
@ -604,7 +607,6 @@ Scope (\_SB.PCI0)
Return Return
} }
/* Request IOM for D3 cold entry sequence. */ /* Request IOM for D3 cold entry sequence. */
/* /*
* FIXME: Remove this workaround after resolving b/244082753 * FIXME: Remove this workaround after resolving b/244082753

18
src/soc/intel/meteorlake/acpi/tcss_dma.asl
View File

@ -28,12 +28,16 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */
Method (_S0W, 0x0) Method (_S0W, 0x0)
{ {
#if CONFIG(D3COLD_SUPPORT) #if CONFIG(D3COLD_SUPPORT)
Return (0x4) Return (0x04)
#else #else
Return (0x3) Return (0x03)
#endif // D3COLD_SUPPORT #endif // D3COLD_SUPPORT
} }
/*
* Get power resources that are dependent on this device for Operating System Power Management
* to put the device in the D0 device state
*/
Method (_PR0) Method (_PR0)
{ {
#if CONFIG(D3COLD_SUPPORT) #if CONFIG(D3COLD_SUPPORT)
@ -48,7 +52,7 @@ Method (_PR0)
} Else { } Else {
Return (Package() { \_SB.PCI0.TBT1 }) Return (Package() { \_SB.PCI0.TBT1 })
} }
#endif // D3COLD_SUPPORT #endif // D3COLD_SUPPORT
} }
Method (_PR3) Method (_PR3)
@ -73,8 +77,8 @@ Method (_PR3)
*/ */
Method (D3CX, 0, Serialized) Method (D3CX, 0, Serialized)
{ {
DD3E = 0 /* Disable DMA RTD3 */ DD3E = 0x00 /* Disable DMA RTD3 */
STAT = 0x1 STAT = 0x01
} }
/* /*
@ -82,8 +86,8 @@ Method (D3CX, 0, Serialized)
*/ */
Method (D3CE, 0, Serialized) Method (D3CE, 0, Serialized)
{ {
DD3E = 1 /* Enable DMA RTD3 */ DD3E = 0x01 /* Enable DMA RTD3 */
STAT = 0 STAT = 0x00
} }
/* /*