soc/amd/common: Add coreboot post codes to STB
Adding coreboot's postcodes to the smart trace buffer lets us see the entire boot flow in one place. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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@ -7,6 +7,7 @@
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#define AMD_STB_PMI_0 0x30600
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#define AMD_STB_PMI_0 0x30600
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#define AMD_STB_COREBOOT_POST_PREFIX 0xBA000000
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#define AMD_STB_COREBOOT_MARKER 0xBAADF00D
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#define AMD_STB_COREBOOT_MARKER 0xBAADF00D
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struct stb_entry_struct {
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struct stb_entry_struct {
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@ -14,4 +14,10 @@ config WRITE_STB_BUFFER_TO_CONSOLE
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points through the boot process. Note that this will prevent the
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points through the boot process. Note that this will prevent the
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entries from being stored if the Spill-to-DRAM feature is enabled.
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entries from being stored if the Spill-to-DRAM feature is enabled.
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config ADD_POSTCODES_TO_STB
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bool "Add coreboot postcodes to STB"
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default y
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help
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Add coreboot's postcodes to the smart trace buffer
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endif
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endif
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@ -18,6 +18,12 @@ static uint32_t stb_read32(uint32_t reg)
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return smn_read32(STB_CFG_SMN_ADDR + reg);
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return smn_read32(STB_CFG_SMN_ADDR + reg);
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}
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}
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void soc_post_code(uint8_t value)
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{
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if (CONFIG(ADD_POSTCODES_TO_STB))
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stb_write32(AMD_STB_PMI_0, AMD_STB_COREBOOT_POST_PREFIX | value);
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}
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void write_stb_to_console(void)
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void write_stb_to_console(void)
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{
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{
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int i;
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int i;
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