GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/cannonlake_rvp: enable HS400 

Set SCS emmc HS400 enable FSP parameter.

TEST=Boot to OS, verify HS400 SDHCI print

Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22008
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
This commit is contained in:
Bora Guvendik 2017-10-13 15:15:48 -07:00 committed by Aaron Durbin
parent de897a6dba
commit 530c6f9cc8
2 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View File

@ -9,6 +9,7 @@ chip soc/intel/cannonlake
register "FspSkipMpInit" = "1" register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1" register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1" register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -9,6 +9,7 @@ chip soc/intel/cannonlake
register "FspSkipMpInit" = "1" register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1" register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1" register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"