soc/intel/quark: Drop support
As announced in the 4.20 release notes, support for the Intel Quark SoC is moved to the 4.20 branch and dropped from master. Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Felix Singer
Felix Singer
parent
037c25d4dd
commit
531023285e
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# SPDX-License-Identifier: GPL-2.0-only
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config SOC_INTEL_QUARK
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bool
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help
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Intel Quark support
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if SOC_INTEL_QUARK
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_NO_CUSTOM_MADT
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select ARCH_X86
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select NO_ECAM_MMCONF_SUPPORT
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select NO_SMM
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select REG_SCRIPT
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select PLATFORM_USES_FSP2_0
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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select SOC_SETS_MSRS
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select SPI_FLASH
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select UART_OVERRIDE_REFCLK
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select UDELAY_TSC
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select TSC_MONOTONIC_TIMER
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select UNCOMPRESSED_RAMSTAGE
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select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
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select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
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select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
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select USE_MARCH_586
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#####
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# Debug serial output
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# The following options configure the debug serial port
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#####
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config ENABLE_BUILTIN_HSUART0
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bool "Enable built-in HSUART0"
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default n
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART0, which can be used for the debug console.
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config ENABLE_BUILTIN_HSUART1
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bool "Enable built-in HSUART1"
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default n
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depends on ! ENABLE_BUILTIN_HSUART0
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select NO_UART_ON_SUPERIO
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select DRIVERS_UART_8250MEM_32
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help
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The Quark SoC has two HSUART. Choose this option to configure the pads
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and enable HSUART1, which can be used for the debug console.
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config TTYS0_BASE
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hex "HSUART Base Address"
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default 0xA0019000
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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help
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Memory mapped MMIO of HSUART.
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config TTYS0_LCS
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int
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default 3
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depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
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#####
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# Debug support
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# The following options provide debug support for the Quark coreboot
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# code. The SD LED is used as a binary marker to determine if a
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# specific point in the execution flow has been reached.
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#####
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config ENABLE_DEBUG_LED
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bool
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default n
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help
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Enable the use of the SD LED for early debugging before serial output
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is available. Setting this LED indicates that control has reached the
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desired check point.
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config ENABLE_DEBUG_LED_ESRAM
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bool "SD LED indicates ESRAM initialized"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that ESRAM has been successfully initialized. If the SD LED
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does not light then the ESRAM initialization needs to be debugged.
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config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
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bool "SD LED indicates bootblock.c successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_c_entry was entered. If the SD LED does not
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light then debug the code between ESRAM and bootblock_c_entry.
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config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
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bool "SD LED indicates bootblock_soc_early_init successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_early_init was entered. If the SD LED
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does not light then debug the code in bootblock_main_with_timestamp.
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config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT
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bool "SD LED indicates bootblock_soc_early_init successfully exited"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_early_init exited. If the SD LED does not
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light then debug the scripts in bootblock_soc_early_init.
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config ENABLE_DEBUG_LED_SOC_INIT_ENTRY
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bool "SD LED indicates bootblock_soc_init successfully entered"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that bootblock_soc_init was entered. If the SD LED does not
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light then debug the code in bootblock_mainboard_early_init and
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console_init. If the SD LED does light but there is no serial then
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debug the serial port configuration and initialization.
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#####
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# ESRAM layout
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# Specify the portion of the ESRAM for coreboot to use as its data area.
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#####
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config DCACHE_RAM_BASE
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hex
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default 0x80000000
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config DCACHE_RAM_SIZE
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hex
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default 0x40000
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config DISPLAY_ESRAM_LAYOUT
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bool "Display ESRAM layout"
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default n
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help
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Select this option to display coreboot's use of ESRAM.
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#####
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# Flash layout
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# Specify the size of the coreboot file system in the read-only
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# (recovery) portion of the flash part.
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#####
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config CBFS_SIZE
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default 0x200000
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help
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Specify the size of the coreboot file system in the read-only (recovery)
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portion of the flash part. On Quark systems the firmware image stores
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more than just coreboot, including:
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- The chipset microcode (RMU) binary file located at 0xFFF00000
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- Intel Trusted Execution Engine firmware
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#####
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# FSP binary
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# The following options control the FSP binary file placement in
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# the flash image and ESRAM. This file is required by the Quark
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# SoC code to boot coreboot and its payload.
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#####
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config FSP_ESRAM_LOC
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hex
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default 0x80040000
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help
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The location in ESRAM where a copy of the FSP binary is placed.
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config FSP_M_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"
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config FSP_S_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"
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#####
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# RMU binary
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# The following options control the Quark chipset microcode file
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# placement in the flash image. This file is required to bring
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# the Quark processor out of reset.
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#####
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config ADD_RMU_FILE
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bool "Should the RMU binary be added to the flash image?"
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default n
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help
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The RMU file is required to get the chip out of reset.
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config RMU_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/rmu.bin"
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depends on ADD_RMU_FILE
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help
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The path and filename of the Intel Quark RMU binary.
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config RMU_LOC
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hex
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default 0xfff00000
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depends on ADD_RMU_FILE
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help
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The location in CBFS that the RMU is located. It must match the
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strap-determined base address.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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#####
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# Test support
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#####
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config STORAGE_TEST
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bool "Test SD/MMC/eMMC card or device access"
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default n
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select COMMONLIB_STORAGE
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select SDHCI_CONTROLLER
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help
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Read block 0 from each partition of the storage device. User
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must also enable one or both of COMMONLIB_STORAGE_SD or
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COMMONLIB_STORAGE_MMC.
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config STORAGE_LOG
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bool "Log and display SD/MMC commands"
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default n
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depends on STORAGE_TEST
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#####
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# I2C debug support
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#####
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config I2C_DEBUG
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bool "Enable I2C debugging"
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default n
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help
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Display the I2C segments and controller errors
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endif # SOC_INTEL_QUARK
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@ -1,72 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
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subdirs-y += romstage
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bootblock-y += bootblock/esram_init.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += i2c.c
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bootblock-y += reg_access.c
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bootblock-y += tsc_freq.c
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bootblock-y += uart_common.c
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verstage-y += i2c.c
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verstage-y += reg_access.c
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verstage-y += tsc_freq.c
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verstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += reg_access.c
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romstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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romstage-y += tsc_freq.c
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romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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romstage-y += reset.c
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postcar-y += fsp_params.c
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postcar-y += i2c.c
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postcar-y += reg_access.c
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postcar-y += tsc_freq.c
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postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += northcluster.c
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ramstage-y += reg_access.c
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ramstage-y += reset.c
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ramstage-y += sd.c
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ramstage-y += spi.c
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ramstage-y += spi_debug.c
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ramstage-$(CONFIG_STORAGE_TEST) += storage_test.c
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ramstage-y += tsc_freq.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
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ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/quark
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CPPFLAGS_common += -I$(src)/soc/intel/quark/include
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# Chipset microcode path
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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# Since FSP-M runs in CAR we need to relocate it to a specific address
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$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_ESRAM_LOC)
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# Add the FSP binary to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := raw
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# Add the chipset microcode file to the CBFS image
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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rmu.bin-position := $(CONFIG_RMU_LOC)
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rmu.bin-type := raw
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endif # CONFIG_SOC_INTEL_QUARK
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@ -1,76 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <soc/acpi.h>
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#include <soc/ramstage.h>
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK)
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& B_QNC_LPC_GPE0BLK_MASK;
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uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK)
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& B_QNC_LPC_PM1BLK_MASK;
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fadt->flags |= ACPI_FADT_PLATFORM_CLOCK;
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/* PM1 Status: ACPI 4.8.3.1.1 */
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fadt->pm1a_evt_blk = pmbase + R_QNC_PM1BLK_PM1S;
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fadt->pm1_evt_len = 2;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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/* PM1 Control: ACPI 4.8.3.2.1 */
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fadt->pm1a_cnt_blk = pmbase + R_QNC_PM1BLK_PM1C;
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fadt->pm1_cnt_len = 2;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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/* PM Timer: ACPI 4.8.3.3 */
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fadt->pm_tmr_blk = pmbase + R_QNC_PM1BLK_PM1T;
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fadt->pm_tmr_len = 4;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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/* General-Purpose Event 0 Registers: ACPI 4.8.4.1 */
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fadt->gpe0_blk = gpe0_base;
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fadt->gpe0_blk_len = 4 * 2;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0x0;
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/* Display the base registers */
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printk(BIOS_SPEW, "FADT:\n");
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printk(BIOS_SPEW, " 0x%08x: GPE0_BASE\n", gpe0_base);
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printk(BIOS_SPEW, " 0x%08x: PMBASE\n", pmbase);
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printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
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}
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uint16_t get_pmbase(void)
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{
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struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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return (uint16_t)pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
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}
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@ -1,109 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <device/pci_def.h>
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#include <program_loading.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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extern asmlinkage void light_sd_led(void);
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static const struct reg_script legacy_gpio_init[] = {
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/* Temporarily enable the legacy GPIO controller */
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REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
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| LEGACY_GPIO_BASE_ADDRESS),
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/* Temporarily enable the GPE controller */
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REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
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| GPE0_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
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REG_SCRIPT_END
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};
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static const struct reg_script i2c_gpio_controller_init[] = {
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/* Temporarily enable the GPIO controller */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script hsuart_init[] = {
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/* Enable the HSUART */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
|
||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script mtrr_init[] = {
|
||||
/* Use write-through caching, for FSP 2.0 the cache will be invalidated
|
||||
* postchar (arch/x86/exit_car.S).
|
||||
*/
|
||||
|
||||
/* Enable the cache */
|
||||
REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)),
|
||||
|
||||
/* Cache the SPI flash */
|
||||
REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE)
|
||||
| MTRR_TYPE_WRTHROUGH)),
|
||||
REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE)
|
||||
| MTRR_PHYS_MASK_VALID)),
|
||||
|
||||
/* Cache ESRAM */
|
||||
REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000
|
||||
| MTRR_TYPE_WRTHROUGH)),
|
||||
REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff)
|
||||
| MTRR_PHYS_MASK_VALID)),
|
||||
|
||||
/* Enable the variable MTRRs */
|
||||
REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN
|
||||
| MTRR_TYPE_UNCACHEABLE),
|
||||
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
|
||||
{
|
||||
if (CONFIG(ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
bootblock_main_with_basetime(base_timestamp);
|
||||
}
|
||||
|
||||
void bootblock_soc_early_init(void)
|
||||
{
|
||||
if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
/* Initialize the MTRRs */
|
||||
reg_script_run(mtrr_init);
|
||||
|
||||
/* Initialize the controllers */
|
||||
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
|
||||
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
|
||||
|
||||
/* Enable the HSUART */
|
||||
if (CONFIG(ENABLE_BUILTIN_HSUART0))
|
||||
reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
|
||||
if (CONFIG(ENABLE_BUILTIN_HSUART1))
|
||||
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
|
||||
|
||||
if (CONFIG(ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT))
|
||||
light_sd_led();
|
||||
}
|
||||
|
||||
void bootblock_soc_init(void)
|
||||
{
|
||||
if (CONFIG(ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
|
||||
light_sd_led();
|
||||
|
||||
display_mtrrs();
|
||||
}
|
||||
|
||||
void platform_prog_run(struct prog *prog)
|
||||
{
|
||||
/* Display the program entry point */
|
||||
printk(BIOS_SPEW, "Calling %s, %p(%p)\n", prog->name,
|
||||
prog->entry, prog->arg);
|
||||
}
|
||||
|
|
@ -1,505 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
|
||||
#include <cpu/x86/cr.h>
|
||||
#include <cpu/x86/post_code.h>
|
||||
#include <soc/QuarkNcSocId.h>
|
||||
#include <soc/sd.h>
|
||||
|
||||
.macro RET32
|
||||
jmp *%esp
|
||||
.endm
|
||||
|
||||
/* ROM/SPI/MEMORY Definitions */
|
||||
.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) /* Memory Base Address = 0 */
|
||||
.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) /* DDR3 Memory Size = 2GB */
|
||||
.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
|
||||
+ QUARK_MAX_DDR3_MEM_SIZE_BYTES) /* eSRAM Memory above DDR3 */
|
||||
.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) /* eSRAM Memory Size = 512K */
|
||||
.equ QUARK_STACK_SIZE_BYTES, (0x008000) /* Quark stack size = 32K */
|
||||
.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
|
||||
+ QUARK_ESRAM_MEM_SIZE_BYTES \
|
||||
- QUARK_STACK_SIZE_BYTES) /* Top of eSRAM - stack size */
|
||||
.equ QUARK_CMH_SIZE_BYTES, (0x0400) /* Quark Module Header size */
|
||||
.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
|
||||
+ QUARK_CMH_SIZE_BYTES) /* Start of Stage1 code in eSRAM */
|
||||
|
||||
/* RTC/CMOS definitions */
|
||||
.equ RTC_INDEX, (0x70)
|
||||
.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */
|
||||
.equ RTC_DATA, (0x71)
|
||||
|
||||
/* PCI Configuration definitions (Datasheet 5.5.1) */
|
||||
.equ PCI_CFG, (0x80000000) /* PCI configuration access mechanism */
|
||||
.equ PCI_ADDRESS_PORT, (0xCF8)
|
||||
.equ PCI_DATA_PORT, (0xCFC)
|
||||
|
||||
/* Quark PCI devices */
|
||||
.equ HOST_BRIDGE_PFA, (0 << 11) /* B0:D0:F0 (Host Bridge) */
|
||||
.equ ILB_PFA, (0x1F << 11) /* B0:D31:F0 (Legacy Block) */
|
||||
|
||||
/* ILB PCI Config Registers */
|
||||
.equ BDE, (0x0D4) /* BIOS Decode Enable register */
|
||||
.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) /* Decode all BIOS ranges */
|
||||
|
||||
/* iLB Reset Register */
|
||||
.equ ILB_RESET_REG, (0x0CF9)
|
||||
.equ CF9_WARM_RESET, (0x02)
|
||||
.equ CF9_COLD_RESET, (0x08)
|
||||
|
||||
/* Memory Arbiter Config Registers */
|
||||
.equ AEC_CTRL_OFFSET, (0x00)
|
||||
|
||||
/* Host Bridge Config Registers */
|
||||
.equ HMBOUND_OFFSET, (0x08)
|
||||
.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
|
||||
+ QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
|
||||
.equ HECREG_OFFSET, (0x09)
|
||||
.equ EC_BASE, (0xE0000000)
|
||||
.equ EC_ENABLE, (0x01)
|
||||
|
||||
/* Memory Manager Config Registers */
|
||||
.equ ESRAM_ADDRESS_2G, (0x10000080)
|
||||
.equ BIMRVCTL_OFFSET, (0x19)
|
||||
.equ ENABLE_IMR_INTERRUPT, (0x80000000)
|
||||
|
||||
/* SOC UNIT Debug Registers */
|
||||
.equ CFGSTICKY_W1_OFFSET, (0x50)
|
||||
.equ FORCE_COLD_RESET, (0x00000001)
|
||||
.equ CFGSTICKY_RW_OFFSET, (0x51)
|
||||
.equ RESET_FOR_ESRAM_LOCK, (0x00000020)
|
||||
.equ RESET_FOR_HMBOUND_LOCK, (0x00000040)
|
||||
.equ CFGNONSTICKY_W1_OFFSET, (0x52)
|
||||
.equ FORCE_WARM_RESET, (0x00000001)
|
||||
|
||||
.section .init, "ax", @progbits
|
||||
|
||||
.global bootblock_pre_c_entry
|
||||
|
||||
bootblock_pre_c_entry:
|
||||
|
||||
/* Get the timestamp since code in bootblock_crt0.S requires
|
||||
* MMX register support.
|
||||
*/
|
||||
rdtsc
|
||||
movl %eax, %ebp
|
||||
movl %edx, %edi
|
||||
|
||||
/* Registers:
|
||||
* ebp: Low 32-bits of timestamp
|
||||
* edi: High 32-bits of timestamp
|
||||
*/
|
||||
|
||||
setup_esram:
|
||||
/* Ensure cache is disabled. */
|
||||
movl %cr0, %eax
|
||||
orl $(CR0_CD | CR0_NW), %eax
|
||||
invd
|
||||
movl %eax, %cr0
|
||||
|
||||
/*
|
||||
* Disable NMI operation
|
||||
* Good convention suggests you should read back RTC data port after
|
||||
* accessing the RTC index port.
|
||||
*/
|
||||
movb $(NMI_DISABLE), %al
|
||||
movw $(RTC_INDEX), %dx
|
||||
outb %al, %dx
|
||||
movw $(RTC_DATA), %dx
|
||||
inb %dx, %al
|
||||
|
||||
/* Disable SMI (Disables SMI wire, not SMI messages) */
|
||||
movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L1, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L1:
|
||||
andl $(~SMI_EN), %eax
|
||||
movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L2, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L2:
|
||||
|
||||
/*
|
||||
* Before we get going, check SOC Unit Registers to see if we are
|
||||
* required to issue a warm/cold reset
|
||||
*/
|
||||
movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L3, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L3:
|
||||
andl $(FORCE_WARM_RESET), %eax
|
||||
jz TestForceColdReset /* No warm reset - branch */
|
||||
jmp IssueWarmReset
|
||||
|
||||
TestForceColdReset:
|
||||
movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L4, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L4:
|
||||
andl $(FORCE_COLD_RESET), %eax
|
||||
jz TestHmboundLock /* No cold reset - branch */
|
||||
jmp IssueColdReset
|
||||
|
||||
/* Before setting HMBOUND, check it's not locked */
|
||||
TestHmboundLock:
|
||||
movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L5, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L5:
|
||||
andl $(HMBOUND_LOCK), %eax
|
||||
jz ConfigHmbound /* Good configuration - branch */
|
||||
|
||||
/* Failed to config - store sticky bit debug */
|
||||
movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L6, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L6:
|
||||
orl $(RESET_FOR_HMBOUND_LOCK), %eax
|
||||
movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L7, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L7:
|
||||
jmp IssueWarmReset
|
||||
|
||||
/* Set up the HMBOUND register */
|
||||
ConfigHmbound:
|
||||
movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */
|
||||
movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L8, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L8:
|
||||
|
||||
/*
|
||||
* Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND
|
||||
* violation occurs.
|
||||
*/
|
||||
movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */
|
||||
movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L9, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L9:
|
||||
|
||||
/* Move eSRAM memory to 2GB */
|
||||
movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */
|
||||
movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
|
||||
<< QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L10, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L10:
|
||||
|
||||
/* Check that we're not blocked from setting the config that we want. */
|
||||
movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
|
||||
<< QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L11, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L11:
|
||||
andl $(BLOCK_ENABLE_PG), %eax
|
||||
jnz ConfigPci /* Good configuration - branch */
|
||||
|
||||
/* Failed to config - store sticky bit debug */
|
||||
movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L12, %esp
|
||||
jmp stackless_SideBand_Read
|
||||
L12:
|
||||
orl $(RESET_FOR_ESRAM_LOCK), %eax
|
||||
movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L13, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L13:
|
||||
jmp IssueWarmReset
|
||||
|
||||
/* Enable PCIEXBAR */
|
||||
ConfigPci:
|
||||
movl $(EC_BASE + EC_ENABLE), %eax /* Data */
|
||||
movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L14, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L14:
|
||||
|
||||
movl $(EC_BASE + EC_ENABLE), %eax /* Data */
|
||||
movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
|
||||
| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
|
||||
| (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
|
||||
leal L15, %esp
|
||||
jmp stackless_SideBand_Write
|
||||
L15:
|
||||
|
||||
/* Open up full 8MB SPI decode */
|
||||
movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */
|
||||
movl $(DECODE_ALL_REGIONS_ENABLE), %eax
|
||||
leal L16, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L16:
|
||||
|
||||
jmp esram_init_done
|
||||
|
||||
IssueWarmReset:
|
||||
/* Issue Warm Reset request to Remote Management Unit via iLB */
|
||||
movw $(CF9_WARM_RESET), %ax
|
||||
movw $(ILB_RESET_REG), %dx
|
||||
outw %ax, %dx
|
||||
jmp . /* Stay here until we are reset. */
|
||||
|
||||
IssueColdReset:
|
||||
/* Issue Cold Reset request to Remote Management Unit via iLB */
|
||||
movw $(CF9_COLD_RESET), %ax
|
||||
movw $(ILB_RESET_REG), %dx
|
||||
outw %ax, %dx
|
||||
jmp . /* Stay here until we are reset. */
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_SideBand_Read
|
||||
*
|
||||
* Input: esp - return address
|
||||
* ecx[15:8] - Register offset
|
||||
* ecx[23:16] - Port ID
|
||||
* ecx[31:24] - Opcode
|
||||
*
|
||||
* Output: eax - Data read
|
||||
*
|
||||
* Destroys: eax
|
||||
* ebx
|
||||
* cl
|
||||
* esi
|
||||
*
|
||||
* Description:
|
||||
* Perform requested sideband read
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_SideBand_Read:
|
||||
|
||||
movl %esp, %esi /* Save the return address */
|
||||
|
||||
/* Load the SideBand Packet Register to generate the transaction */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
|
||||
movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
|
||||
xchgl %ecx, %eax
|
||||
leal L17, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L17:
|
||||
xchgl %ecx, %eax
|
||||
|
||||
/* Read the SideBand Data Register */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx
|
||||
leal L18, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
L18:
|
||||
|
||||
movl %esi, %esp /* Restore the return address */
|
||||
RET32
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_SideBand_Write
|
||||
*
|
||||
* Input: esp - return address
|
||||
* eax - Data
|
||||
* ecx[15:8] - Register offset
|
||||
* ecx[23:16] - Port ID
|
||||
* ecx[31:24] - Opcode
|
||||
*
|
||||
* Output: None
|
||||
*
|
||||
* Destroys: ebx
|
||||
* cl
|
||||
* esi
|
||||
*
|
||||
* Description:
|
||||
* Perform requested sideband write
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_SideBand_Write:
|
||||
|
||||
movl %esp, %esi /* Save the return address */
|
||||
|
||||
/* Load the SideBand Data Register with the data */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx
|
||||
leal L19, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L19:
|
||||
|
||||
/* Load the SideBand Packet Register to generate the transaction */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
|
||||
movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
|
||||
xchgl %ecx, %eax
|
||||
leal L20, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L20:
|
||||
xchgl %ecx, %eax
|
||||
|
||||
movl %esi, %esp /* Restore the return address */
|
||||
RET32
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_PCIConfig_Write
|
||||
*
|
||||
* Input: esp - return address
|
||||
* eax - Data to write
|
||||
* ebx - PCI Config Address
|
||||
*
|
||||
* Output: None
|
||||
*
|
||||
* Destroys: dx
|
||||
*
|
||||
* Description:
|
||||
* Perform a DWORD PCI Configuration write
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_PCIConfig_Write:
|
||||
|
||||
/* Write the PCI Config Address to the address port */
|
||||
xchgl %ebx, %eax
|
||||
movw $(PCI_ADDRESS_PORT), %dx
|
||||
outl %eax, %dx
|
||||
xchgl %ebx, %eax
|
||||
|
||||
/* Write the PCI DWORD Data to the data port */
|
||||
movw $(PCI_DATA_PORT), %dx
|
||||
outl %eax, %dx
|
||||
|
||||
RET32
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_PCIConfig_Read
|
||||
*
|
||||
* Input: esp - return address
|
||||
* ebx - PCI Config Address
|
||||
*
|
||||
* Output: eax - Data read
|
||||
*
|
||||
* Destroys: eax
|
||||
* dx
|
||||
*
|
||||
* Description:
|
||||
* Perform a DWORD PCI Configuration read
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_PCIConfig_Read:
|
||||
|
||||
/* Write the PCI Config Address to the address port */
|
||||
xchgl %ebx, %eax
|
||||
movw $(PCI_ADDRESS_PORT), %dx
|
||||
outl %eax, %dx
|
||||
xchgl %ebx, %eax
|
||||
|
||||
/* Read the PCI DWORD Data from the data port */
|
||||
movw $(PCI_DATA_PORT), %dx
|
||||
inl %dx, %eax
|
||||
|
||||
RET32
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
esram_init_done:
|
||||
|
||||
#if CONFIG(ENABLE_DEBUG_LED)
|
||||
sd_led:
|
||||
|
||||
/* Set the SDIO controller's base address */
|
||||
movl $(SD_BASE_ADDR), %eax
|
||||
movl $(SD_CFG_ADDR), %ebx
|
||||
leal L40, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
|
||||
L40:
|
||||
movl $(SD_CFG_ADDR), %ebx
|
||||
leal L41, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
|
||||
L41:
|
||||
/* Enable the SDIO controller */
|
||||
movl $(SD_CFG_CMD), %ebx
|
||||
leal L42, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
|
||||
L42:
|
||||
orl $2, %eax
|
||||
movl $(SD_CFG_CMD), %ebx
|
||||
leal L43, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
|
||||
L43:
|
||||
movl $(SD_CFG_CMD), %ebx
|
||||
leal L44, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
|
||||
L44:
|
||||
#if CONFIG(ENABLE_DEBUG_LED_ESRAM)
|
||||
jmp light_sd_led
|
||||
#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
|
||||
#endif /* CONFIG_ENABLE_DEBUG_LED */
|
||||
|
||||
/* Registers:
|
||||
* ebp: Low 32-bits of timestamp
|
||||
* edi: High 32-bits of timestamp
|
||||
*/
|
||||
|
||||
/* Setup bootblock stack */
|
||||
movl $_ecar_stack, %esp
|
||||
|
||||
before_carstage:
|
||||
post_code(0x2b)
|
||||
|
||||
/* Get the timestamp passed in bootblock_crt0.S */
|
||||
push %edi
|
||||
push %ebp
|
||||
|
||||
/* We can call into C functions now */
|
||||
call bootblock_c_entry
|
||||
|
||||
/* Never reached */
|
||||
|
||||
.global light_sd_led
|
||||
|
||||
light_sd_led:
|
||||
/* Turn on SD LED to indicate ESRAM successfully initialized */
|
||||
movl $SD_HOST_CTRL, %ebx
|
||||
movb 0(%ebx), %al
|
||||
orb $1, %al
|
||||
movb %al, 0(%ebx)
|
||||
|
||||
/* Loop forever */
|
||||
die:
|
||||
hlt
|
||||
jmp die
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <device/device.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
/* Cat Trip Clear value must be less than Cat Trip Set value */
|
||||
#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105
|
||||
#define PLATFORM_CATASTROPHIC_CLEAR_CELSIUS 65
|
||||
|
||||
static const struct reg_script thermal_init_script[] = {
|
||||
|
||||
/* Setup RMU Thermal sensor registers for Ratiometric mode. */
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG,
|
||||
~(B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK
|
||||
| B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK
|
||||
| B_TSCGF1_CONFIG_ISNSINTERNALVREFEN
|
||||
| B_TSCGF1_CONFIG_IBGEN
|
||||
| B_TSCGF1_CONFIG_IBGCHOPEN),
|
||||
((V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP)
|
||||
| (V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_ISNSCHOPSEL_BP)
|
||||
| (V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP)
|
||||
| (V_TSCGF1_CONFIG_IBGEN_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_IBGEN_BP)
|
||||
| (V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE
|
||||
<< B_TSCGF1_CONFIG_IBGCHOPEN_BP))),
|
||||
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2,
|
||||
~(B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK
|
||||
| B_TSCGF2_CONFIG2_ISPARECTRL_MASK
|
||||
| B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK),
|
||||
((V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP)
|
||||
| (V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG2_ISPARECTRL_BP)
|
||||
| (V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP))),
|
||||
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG,
|
||||
~(B_TSCGF2_CONFIG_IDSCONTROL_MASK
|
||||
| B_TSCGF2_CONFIG_IDSTIMING_MASK),
|
||||
((V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG_IDSCONTROL_BP)
|
||||
| (V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE
|
||||
<< B_TSCGF2_CONFIG_IDSTIMING_BP))),
|
||||
|
||||
REG_SOC_UNIT_RMW(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
|
||||
~B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK,
|
||||
V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE
|
||||
<< B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP),
|
||||
|
||||
/* Enable RMU Thermal sensor with a Catastrophic Trip point. */
|
||||
|
||||
/* Set up Catastrophic Trip point.
|
||||
*
|
||||
* Trip Register fields are 8-bit temperature values of granularity 1
|
||||
* degree C where 0x00 corresponds to -50 degrees C and 0xFF corresponds
|
||||
* to 205 degrees C.
|
||||
*
|
||||
* Add 50 to Celsius values to get values for register fields.
|
||||
*/
|
||||
REG_RMU_TEMP_RMW(QUARK_NC_RMU_REG_TS_TRIP,
|
||||
~(TS_CAT_TRIP_SET_THOLD_MASK | TS_CAT_TRIP_CLEAR_THOLD_MASK),
|
||||
(((PLATFORM_CATASTROPHIC_TRIP_CELSIUS + 50)
|
||||
<< TS_CAT_TRIP_SET_THOLD_BP)
|
||||
| ((PLATFORM_CATASTROPHIC_CLEAR_CELSIUS + 50)
|
||||
<< TS_CAT_TRIP_CLEAR_THOLD_BP))),
|
||||
|
||||
/* To enable the TS do the following:
|
||||
* 1) Take the TS out of reset by setting itsrst to 0x0.
|
||||
* 2) Enable the TS using RMU Thermal sensor mode register.
|
||||
*/
|
||||
REG_SOC_UNIT_AND(QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG,
|
||||
~B_TSCGF3_CONFIG_ITSRST),
|
||||
REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_TS_MODE, TS_ENABLE),
|
||||
|
||||
/* Lock all RMU Thermal sensor control & trip point registers. */
|
||||
REG_RMU_TEMP_OR(QUARK_NC_RMU_REG_CONFIG, TS_LOCK_THRM_CTRL_REGS_ENABLE
|
||||
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static void chip_init(void *chip_info)
|
||||
{
|
||||
/* Validate the temperature settings */
|
||||
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255);
|
||||
ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS
|
||||
> PLATFORM_CATASTROPHIC_CLEAR_CELSIUS);
|
||||
|
||||
/* Set the temperature settings */
|
||||
reg_script_run(thermal_init_script);
|
||||
|
||||
/* Verify that the thermal configuration is locked */
|
||||
ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG)
|
||||
& (TS_LOCK_THRM_CTRL_REGS_ENABLE
|
||||
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE))
|
||||
== (TS_LOCK_THRM_CTRL_REGS_ENABLE
|
||||
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
|
||||
|
||||
/* Perform silicon specific init. */
|
||||
fsp_silicon_init();
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
static void chip_enable_dev(struct device *dev)
|
||||
{
|
||||
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN)
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
|
||||
struct chip_operations soc_intel_quark_ops = {
|
||||
CHIP_NAME("Intel Quark")
|
||||
.init = &chip_init,
|
||||
.enable_dev = chip_enable_dev,
|
||||
};
|
||||
|
|
@ -1,101 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_CHIP_H_
|
||||
#define _SOC_CHIP_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <fsp/util.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
|
||||
///
|
||||
/// MRC Flags bits
|
||||
///
|
||||
#define MRC_FLAG_ECC_EN BIT0
|
||||
#define MRC_FLAG_SCRAMBLE_EN BIT1
|
||||
#define MRC_FLAG_MEMTEST_EN BIT2
|
||||
|
||||
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
|
||||
#define MRC_FLAG_TOP_TREE_EN BIT3
|
||||
|
||||
/* If set ODR signal is asserted to DRAM devices on writes */
|
||||
#define MRC_FLAG_WR_ODT_EN BIT4
|
||||
|
||||
struct soc_intel_quark_config {
|
||||
/*
|
||||
* MemoryInit:
|
||||
*
|
||||
* The following fields come from FspUpdVpd.h and are defined as PCDs
|
||||
* for the FSP binary. Data for these fields comes from the board's
|
||||
* devicetree.cb file which gets processed into static.c and then
|
||||
* built into the coreboot image. The fields below contain retain
|
||||
* the FSP PCD field name.
|
||||
*/
|
||||
|
||||
uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */
|
||||
|
||||
uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */
|
||||
uint32_t tRAS; /* ACT to PRE command period in picoseconds */
|
||||
|
||||
/* Delay from start of internal write transaction to internal read
|
||||
* command in picoseconds
|
||||
*/
|
||||
uint32_t tWTR;
|
||||
|
||||
/* ACT to ACT command period (JESD79 specific to page size 1K/2K) in
|
||||
* picoseconds
|
||||
*/
|
||||
uint32_t tRRD;
|
||||
|
||||
/* Four activate window (JESD79 specific to page size 1K/2K) in
|
||||
* picoseconds
|
||||
*/
|
||||
uint32_t tFAW;
|
||||
uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */
|
||||
|
||||
/* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU
|
||||
* support 1066 memory
|
||||
*/
|
||||
uint8_t DramSpeed;
|
||||
uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */
|
||||
|
||||
/* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */
|
||||
uint8_t RankMask;
|
||||
uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */
|
||||
uint8_t ChanWidth; /* 1=x16, others=RESERVED */
|
||||
|
||||
/* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */
|
||||
uint8_t AddrMode;
|
||||
|
||||
/* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */
|
||||
uint8_t SrInt;
|
||||
uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */
|
||||
|
||||
/* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver
|
||||
* impedance control.
|
||||
*/
|
||||
uint8_t DramRonVal;
|
||||
uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */
|
||||
uint8_t DramRttWrVal; /* 0=off others=RESERVED */
|
||||
|
||||
/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */
|
||||
uint8_t SocRdOdtVal;
|
||||
uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */
|
||||
uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */
|
||||
|
||||
/* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */
|
||||
uint8_t DramDensity;
|
||||
uint8_t tCL; /* DRAM CAS Latency in clocks */
|
||||
|
||||
/* ECC scrub interval in milliseconds 1..255 (0 works as feature
|
||||
* disable)
|
||||
*/
|
||||
uint8_t EccScrubInterval;
|
||||
|
||||
/* Number of 32B blocks read for ECC scrub 2..16 */
|
||||
uint8_t EccScrubBlkSize;
|
||||
|
||||
uint8_t SmmTsegSize; /* SMM size in MiB */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
/* USB Phy Registers */
|
||||
#define USB2_GLOBAL_PORT 0x4001
|
||||
#define USB2_PLL1 0x7F02
|
||||
#define USB2_PLL2 0x7F03
|
||||
#define USB2_COMPBG 0x7F04
|
||||
|
||||
/* EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs */
|
||||
#define EHCI_OUT_THRESHOLD_VALUE 0x7f
|
||||
#define EHCI_IN_THRESHOLD_VALUE 0x7f
|
||||
|
||||
/* Platform init USB device interrupt masks */
|
||||
#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f)
|
||||
#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG \
|
||||
(B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK \
|
||||
| B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
|
||||
|
||||
/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
|
||||
* reference clock and Port2 as a USB device port, the following sequence must
|
||||
* be followed
|
||||
*/
|
||||
static const struct reg_script ehci_init_script[] = {
|
||||
|
||||
/* Set packet buffer OUT/IN thresholds */
|
||||
REG_MMIO_RMW32(R_IOH_EHCI_INSNREG01,
|
||||
~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
|
||||
| B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK),
|
||||
(EHCI_OUT_THRESHOLD_VALUE
|
||||
<< B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
|
||||
| (EHCI_IN_THRESHOLD_VALUE
|
||||
<< B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)),
|
||||
|
||||
/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
|
||||
* For port 0 & 1 as host and port 2 as device.
|
||||
*/
|
||||
REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
|
||||
|
||||
/*
|
||||
* Sighting #4930653 Required BIOS change on Disconnect vref to change
|
||||
* to 600mV.
|
||||
*/
|
||||
REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
|
||||
(BIT10 | BIT7)),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* (pllbypass) to bypass/Disable PLL before switch
|
||||
*/
|
||||
REG_USB_OR(USB2_PLL2, BIT29),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
|
||||
* (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
|
||||
*/
|
||||
REG_USB_OR(USB2_PLL1, BIT1),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* (divide by 8) to achieve internal 480MHz clock
|
||||
* for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
|
||||
*/
|
||||
REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* Clear (pllbypass)
|
||||
*/
|
||||
REG_USB_AND(USB2_PLL2, ~BIT29),
|
||||
|
||||
/* Sideband register write to USB AFE (Phy)
|
||||
* Set (startlock) to force the PLL FSM to restart the lock
|
||||
* sequence due to input clock/freq switch.
|
||||
*/
|
||||
REG_USB_OR(USB2_PLL2, BIT24),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script usb_device_port_init_script[] = {
|
||||
|
||||
/* Mask and clear controller interrupts */
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,
|
||||
V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG),
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_D_INTR_UDC_REG,
|
||||
V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG),
|
||||
|
||||
/* Mask and clear end point interrupts */
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,
|
||||
V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG),
|
||||
REG_MMIO_WRITE32(R_IOH_USBDEVICE_EP_INTR_UDC_REG,
|
||||
V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
if ((dev->path.pci.devfn & 7) == EHCI_FUNC) {
|
||||
printk(BIOS_INFO, "Initializing USB PLLs\n");
|
||||
reg_script_run_on_dev(dev, ehci_init_script);
|
||||
} else {
|
||||
printk(BIOS_INFO, "Initializing USB device port\n");
|
||||
reg_script_run_on_dev(dev, usb_device_port_init_script);
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = init,
|
||||
};
|
||||
|
||||
static const struct pci_driver driver __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = EHCI_DEVID,
|
||||
};
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
|
||||
{
|
||||
}
|
||||
|
||||
asmlinkage void chipset_teardown_car(void)
|
||||
{
|
||||
}
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
__weak void mainboard_gpio_i2c_init(struct device *dev)
|
||||
{
|
||||
/* Initialize any of the GPIOs or I2C devices */
|
||||
printk(BIOS_SPEW, "WEAK; %s\n", __func__);
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = mainboard_gpio_i2c_init,
|
||||
};
|
||||
|
||||
static const struct pci_driver gfx_driver __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = I2CGPIO_DEVID,
|
||||
};
|
||||
|
|
@ -1,357 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/device.h>
|
||||
#include <device/i2c_simple.h>
|
||||
#include <device/pci.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
#include <timer.h>
|
||||
|
||||
static void i2c_disable(I2C_REGS *regs)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t timeout;
|
||||
|
||||
/* Disable I2C controller */
|
||||
regs->ic_enable = 0;
|
||||
|
||||
/* Wait for the enable bit to clear */
|
||||
timeout = 1 * 1000 * 1000;
|
||||
status = regs->ic_enable_status;
|
||||
while (status & IC_ENABLE_CONTROLLER) {
|
||||
udelay(1);
|
||||
if (--timeout == 0)
|
||||
die_with_post_code(POST_HW_INIT_FAILURE,
|
||||
"ERROR - I2C failed to disable!\n");
|
||||
status = regs->ic_enable_status;
|
||||
}
|
||||
|
||||
/* Clear any pending interrupts */
|
||||
status = regs->ic_clr_intr;
|
||||
}
|
||||
|
||||
static int platform_i2c_write(uint32_t restart, uint8_t *tx_buffer, int length,
|
||||
uint32_t stop, uint8_t *rx_buffer, struct stopwatch *timeout)
|
||||
{
|
||||
int bytes_transferred;
|
||||
uint32_t cmd;
|
||||
I2C_REGS *regs;
|
||||
uint32_t status;
|
||||
|
||||
ASSERT(tx_buffer != NULL);
|
||||
ASSERT(timeout != NULL);
|
||||
regs = get_i2c_address();
|
||||
|
||||
/* Fill the FIFO with the write operation */
|
||||
bytes_transferred = 0;
|
||||
do {
|
||||
status = regs->ic_raw_intr_stat;
|
||||
|
||||
/* Check for errors */
|
||||
if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
|
||||
| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
|
||||
i2c_disable(regs);
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C write error!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout */
|
||||
if (stopwatch_expired(timeout)) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C write timeout!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Receive any available data */
|
||||
status = regs->ic_status;
|
||||
if (rx_buffer != NULL) {
|
||||
while (status & IC_STATUS_RFNE) {
|
||||
*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
|
||||
bytes_transferred++;
|
||||
status = regs->ic_status;
|
||||
}
|
||||
}
|
||||
|
||||
/* Determine if space is available in the FIFO */
|
||||
if (status & IC_STATUS_TFNF) {
|
||||
/* End of the transaction? */
|
||||
cmd = IC_DATA_CMD_WRITE | *tx_buffer++ | restart;
|
||||
if (length == 1)
|
||||
cmd |= stop;
|
||||
restart = 0;
|
||||
|
||||
/* Place a data byte into the FIFO */
|
||||
regs->ic_data_cmd = cmd;
|
||||
length--;
|
||||
bytes_transferred++;
|
||||
} else
|
||||
udelay(1);
|
||||
} while (length > 0);
|
||||
return bytes_transferred;
|
||||
}
|
||||
|
||||
static int platform_i2c_read(uint32_t restart, uint8_t *rx_buffer, int length,
|
||||
uint32_t stop, struct stopwatch *timeout)
|
||||
{
|
||||
int bytes_transferred;
|
||||
uint32_t cmd;
|
||||
int fifo_bytes;
|
||||
I2C_REGS *regs;
|
||||
uint32_t status;
|
||||
|
||||
ASSERT(rx_buffer != NULL);
|
||||
ASSERT(timeout != NULL);
|
||||
regs = get_i2c_address();
|
||||
|
||||
/* Empty the FIFO */
|
||||
status = regs->ic_status;
|
||||
while (status & IC_STATUS_RFNE) {
|
||||
(void)regs->ic_data_cmd;
|
||||
status = regs->ic_status;
|
||||
}
|
||||
|
||||
/* Fill the FIFO with read commands */
|
||||
fifo_bytes = MIN(length, 16);
|
||||
bytes_transferred = 0;
|
||||
while (length > 0) {
|
||||
status = regs->ic_raw_intr_stat;
|
||||
|
||||
/* Check for errors */
|
||||
if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
|
||||
| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
|
||||
i2c_disable(regs);
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read error!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout */
|
||||
if (stopwatch_expired(timeout)) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read timeout!\n",
|
||||
status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Receive any available data */
|
||||
status = regs->ic_status;
|
||||
if (status & IC_STATUS_RFNE) {
|
||||
/* Save the next data byte, removed from the RX FIFO */
|
||||
*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
|
||||
bytes_transferred++;
|
||||
}
|
||||
|
||||
if ((status & IC_STATUS_TFNF)
|
||||
|| ((status & IC_STATUS_RFNE) && (fifo_bytes > 0))) {
|
||||
/* End of the transaction? */
|
||||
cmd = IC_DATA_CMD_READ | restart;
|
||||
if (length == 1)
|
||||
cmd |= stop;
|
||||
restart = 0;
|
||||
|
||||
/* Place a read command into the TX FIFO */
|
||||
regs->ic_data_cmd = cmd;
|
||||
if (fifo_bytes > 0)
|
||||
fifo_bytes--;
|
||||
length--;
|
||||
} else
|
||||
udelay(1);
|
||||
}
|
||||
return bytes_transferred;
|
||||
}
|
||||
|
||||
int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segment,
|
||||
int seg_count)
|
||||
{
|
||||
int bytes_transferred;
|
||||
uint8_t chip;
|
||||
uint32_t cmd;
|
||||
int data_bytes;
|
||||
int index;
|
||||
int length;
|
||||
I2C_REGS *regs;
|
||||
uint32_t restart;
|
||||
uint8_t *rx_buffer;
|
||||
uint32_t status;
|
||||
uint32_t stop;
|
||||
struct stopwatch timeout;
|
||||
int total_bytes;
|
||||
uint8_t *tx_buffer;
|
||||
int tx_bytes;
|
||||
|
||||
if (CONFIG(I2C_DEBUG)) {
|
||||
for (index = 0; index < seg_count;) {
|
||||
if (index == 0)
|
||||
printk(BIOS_ERR, "I2C Start\n");
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d]: %s 0x%02x %s %p, 0x%08x bytes\n",
|
||||
index,
|
||||
(segment[index].flags & I2C_M_RD) ? "Read from" : "Write to",
|
||||
segment[index].slave,
|
||||
(segment[index].flags & I2C_M_RD) ? "to " : "from",
|
||||
segment[index].buf,
|
||||
segment[index].len);
|
||||
printk(BIOS_ERR, "I2C %s\n",
|
||||
(++index >= seg_count) ? "Stop" : "Restart");
|
||||
}
|
||||
}
|
||||
|
||||
regs = get_i2c_address();
|
||||
|
||||
/* Disable the I2C controller to get access to the registers */
|
||||
i2c_disable(regs);
|
||||
|
||||
/* Set the slave address */
|
||||
ASSERT(seg_count > 0);
|
||||
ASSERT(segment != NULL);
|
||||
|
||||
/* Clear the start and stop detection */
|
||||
status = regs->ic_clr_start_det;
|
||||
status = regs->ic_clr_stop_det;
|
||||
|
||||
/* Set addressing mode to 7-bit and fast mode */
|
||||
cmd = regs->ic_con;
|
||||
cmd &= ~(IC_CON_10B | IC_CON_SPEED);
|
||||
cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_400_KHz
|
||||
| IC_CON_MASTER_MODE;
|
||||
regs->ic_con = cmd;
|
||||
|
||||
/* Set the target chip address */
|
||||
chip = segment->slave;
|
||||
regs->ic_tar = chip;
|
||||
|
||||
/* Enable the I2C controller */
|
||||
regs->ic_enable = IC_ENABLE_CONTROLLER;
|
||||
|
||||
/* Clear the interrupts */
|
||||
status = regs->ic_clr_rx_under;
|
||||
status = regs->ic_clr_rx_over;
|
||||
status = regs->ic_clr_tx_over;
|
||||
status = regs->ic_clr_tx_abrt;
|
||||
|
||||
/* Start the timeout */
|
||||
stopwatch_init_usecs_expire(&timeout, CONFIG_I2C_TRANSFER_TIMEOUT_US);
|
||||
|
||||
/* Process each of the segments */
|
||||
total_bytes = 0;
|
||||
tx_bytes = 0;
|
||||
bytes_transferred = 0;
|
||||
rx_buffer = NULL;
|
||||
restart = 0;
|
||||
index = 0;
|
||||
while (index++ < seg_count) {
|
||||
length = segment->len;
|
||||
total_bytes += length;
|
||||
ASSERT(segment->buf != NULL);
|
||||
ASSERT(length >= 1);
|
||||
ASSERT(segment->slave == chip);
|
||||
|
||||
/* Determine if this is the last segment of the transaction */
|
||||
stop = (index == seg_count) ? IC_DATA_CMD_STOP : 0;
|
||||
|
||||
/* Fill the FIFO with the necessary command bytes */
|
||||
if (segment->flags & I2C_M_RD) {
|
||||
/* Place read commands into the FIFO */
|
||||
rx_buffer = segment->buf;
|
||||
data_bytes = platform_i2c_read(restart, rx_buffer,
|
||||
length, stop, &timeout);
|
||||
|
||||
/* Return any detected error */
|
||||
if (data_bytes < 0) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
index);
|
||||
return data_bytes;
|
||||
}
|
||||
bytes_transferred += data_bytes;
|
||||
} else {
|
||||
/* Write the data into the FIFO */
|
||||
tx_buffer = segment->buf;
|
||||
tx_bytes += length;
|
||||
data_bytes = platform_i2c_write(restart, tx_buffer,
|
||||
length, stop, rx_buffer, &timeout);
|
||||
|
||||
/* Return any detected error */
|
||||
if (data_bytes < 0) {
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
index);
|
||||
return data_bytes;
|
||||
}
|
||||
bytes_transferred += data_bytes;
|
||||
}
|
||||
segment++;
|
||||
restart = IC_DATA_CMD_RESTART;
|
||||
}
|
||||
|
||||
/* Wait for the end of the transaction */
|
||||
if (rx_buffer != NULL)
|
||||
rx_buffer += bytes_transferred - tx_bytes;
|
||||
do {
|
||||
/* Receive any available data */
|
||||
status = regs->ic_status;
|
||||
if ((rx_buffer != NULL) && (status & IC_STATUS_RFNE)) {
|
||||
*rx_buffer++ = (uint8_t)regs->ic_data_cmd;
|
||||
bytes_transferred++;
|
||||
} else {
|
||||
status = regs->ic_raw_intr_stat;
|
||||
if ((total_bytes == bytes_transferred)
|
||||
&& (status & IC_INTR_STOP_DET))
|
||||
break;
|
||||
|
||||
/* Check for errors */
|
||||
if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
|
||||
| IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) {
|
||||
i2c_disable(regs);
|
||||
if (CONFIG(I2C_DEBUG)) {
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read error!\n",
|
||||
status);
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
seg_count - 1);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout */
|
||||
if (stopwatch_expired(&timeout)) {
|
||||
if (CONFIG(I2C_DEBUG)) {
|
||||
printk(BIOS_ERR,
|
||||
"0x%08x: ic_raw_intr_stat, I2C read timeout!\n",
|
||||
status);
|
||||
printk(BIOS_ERR,
|
||||
"I2C segment[%d] failed\n",
|
||||
seg_count - 1);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Delay for a while */
|
||||
udelay(1);
|
||||
}
|
||||
} while (1);
|
||||
i2c_disable(regs);
|
||||
regs->ic_tar = 0;
|
||||
|
||||
/* Return the number of bytes transferred */
|
||||
if (CONFIG(I2C_DEBUG))
|
||||
printk(BIOS_ERR, "0x%08x: bytes transferred\n",
|
||||
bytes_transferred);
|
||||
return bytes_transferred;
|
||||
}
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
/* Some configuration of QNC Package */
|
||||
|
||||
#ifndef __INTEL_QNC_CONFIG_H__
|
||||
#define __INTEL_QNC_CONFIG_H__
|
||||
|
||||
//
|
||||
// QNC Fixed configurations.
|
||||
//
|
||||
|
||||
//
|
||||
// Memory arbiter fixed config values.
|
||||
//
|
||||
#define QNC_FIXED_CONFIG_ASTATUS ((UINT32) (\
|
||||
(ASTATUS_PRI_NORMAL << ASTATUS0_DEFAULT_BP) | \
|
||||
(ASTATUS_PRI_NORMAL << ASTATUS1_DEFAULT_BP) | \
|
||||
(ASTATUS_PRI_URGENT << ASTATUS0_RASISED_BP) | \
|
||||
(ASTATUS_PRI_URGENT << ASTATUS1_RASISED_BP) \
|
||||
))
|
||||
|
||||
//
|
||||
// Memory Manager fixed config values.
|
||||
//
|
||||
#define V_DRAM_NON_HOST_RQ_LIMIT 2
|
||||
|
||||
//
|
||||
// RMU Thermal config fixed config values for TS in Vref Mode.
|
||||
//
|
||||
#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_VREF_MODE 0x04
|
||||
#define V_TSCGF2_CONFIG2_ISPARECTRL_VREF_MODE 0x01
|
||||
#define V_TSCGF1_CONFIG_IBGEN_VREF_MODE 1
|
||||
#define V_TSCGF2_CONFIG_IDSCONTROL_VREF_MODE 0x011b
|
||||
#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_VREF_MODE 0x34
|
||||
|
||||
//
|
||||
// RMU Thermal config fixed config values for TS in Ratiometric mode.
|
||||
//
|
||||
#define V_TSCGF1_CONFIG_ISNSCURRENTSEL_RATIO_MODE 0x04
|
||||
#define V_TSCGF1_CONFIG_ISNSCHOPSEL_RATIO_MODE 0x02
|
||||
#define V_TSCGF1_CONFIG_ISNSINTERNALVREFEN_RATIO_MODE 1
|
||||
#define V_TSCGF2_CONFIG_IDSCONTROL_RATIO_MODE 0x011f
|
||||
#define V_TSCGF2_CONFIG_IDSTIMING_RATIO_MODE 0x0001
|
||||
#define V_TSCGF2_CONFIG2_ICALCONFIGSEL_RATIO_MODE 0x01
|
||||
#define V_TSCGF2_CONFIG2_ISPARECTRL_RATIO_MODE 0x00
|
||||
#define V_TSCGF1_CONFIG_IBGEN_RATIO_MODE 0
|
||||
#define V_TSCGF1_CONFIG_IBGCHOPEN_RATIO_MODE 0
|
||||
#define V_TSCGF3_CONFIG_ITSGAMMACOEFF_RATIO_MODE 0xC8
|
||||
#define V_TSCGF2_CONFIG2_ICALCOARSETUNE_RATIO_MODE 0x17
|
||||
|
||||
//
|
||||
// iCLK fixed config values.
|
||||
//
|
||||
#define V_MUXTOP_FLEX2 3
|
||||
#define V_MUXTOP_FLEX1 1
|
||||
|
||||
//
|
||||
// PCIe Root Port fixed config values.
|
||||
//
|
||||
#define V_PCIE_ROOT_PORT_SBIC_VALUE (B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER)
|
||||
|
||||
#endif
|
||||
|
|
@ -1,244 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
#ifndef _IOH_H_
|
||||
#define _IOH_H_
|
||||
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x01
|
||||
#define BIT1 0x02
|
||||
#define BIT2 0x04
|
||||
#define BIT3 0x08
|
||||
#define BIT4 0x10
|
||||
#define BIT5 0x20
|
||||
#define BIT6 0x40
|
||||
#define BIT7 0x80
|
||||
#define BIT8 0x100
|
||||
#define BIT9 0x200
|
||||
#define BIT00 0x00000001
|
||||
#define BIT01 0x00000002
|
||||
#define BIT02 0x00000004
|
||||
#define BIT03 0x00000008
|
||||
#define BIT04 0x00000010
|
||||
#define BIT05 0x00000020
|
||||
#define BIT06 0x00000040
|
||||
#define BIT07 0x00000080
|
||||
#define BIT08 0x00000100
|
||||
#define BIT09 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#endif
|
||||
|
||||
#define IOH_PCI_CFG_ADDRESS(bus, dev, func, reg) \
|
||||
(((UINT32) ((((UINTN)bus) << 24) + (((UINTN)dev) << 16) + \
|
||||
(((UINTN)func) << 8) + ((UINTN)reg))) & 0x00000000ffffffff)
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
#define INTEL_VENDOR_ID 0x8086 // Intel Vendor ID
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Pci Configuration Map Register Offsets
|
||||
//----------------------------------------------------------------------------
|
||||
#define PCI_REG_VID 0x00 // Vendor ID Register
|
||||
#define PCI_REG_DID 0x02 // Device ID Register
|
||||
#define PCI_REG_PCICMD 0x04 // PCI Command Register
|
||||
#define PCI_REG_PCISTS 0x06 // PCI Status Register
|
||||
#define PCI_REG_RID 0x08 // PCI Revision ID Register
|
||||
#define PCI_REG_PI 0x09 // Programming Interface
|
||||
#define PCI_REG_SCC 0x0a // Sub Class Code Register
|
||||
#define PCI_REG_BCC 0x0b // Base Class Code Register
|
||||
#define PCI_REG_PMLT 0x0d // Primary Master Latnecy Timer
|
||||
#define PCI_REG_HDR 0x0e // Header Type Register
|
||||
#define PCI_REG_PBUS 0x18 // Primary Bus Number Register
|
||||
#define PCI_REG_SBUS 0x19 // Secondary Bus Number Register
|
||||
#define PCI_REG_SUBUS 0x1a // Subordinate Bus Number Register
|
||||
#define PCI_REG_SMLT 0x1b // Secondary Master Latnecy Timer
|
||||
#define PCI_REG_IOBASE 0x1c // I/O base Register
|
||||
#define PCI_REG_IOLIMIT 0x1d // I/O Limit Register
|
||||
#define PCI_REG_SECSTATUS 0x1e // Secondary Status Register
|
||||
#define PCI_REG_MEMBASE 0x20 // Memory Base Register
|
||||
#define PCI_REG_MEMLIMIT 0x22 // Memory Limit Register
|
||||
#define PCI_REG_PRE_MEMBASE 0x24 // Prefretchable memory Base register
|
||||
#define PCI_REG_PRE_MEMLIMIT 0x26 // Prefretchable memory Limit register
|
||||
#define PCI_REG_SVID0 0x2c // Subsystem Vendor ID low byte
|
||||
#define PCI_REG_SVID1 0x2d // Subsystem Vendor ID high byte
|
||||
#define PCI_REG_SID0 0x2e // Subsystem ID low byte
|
||||
#define PCI_REG_SID1 0x2f // Subsystem ID high byte
|
||||
#define PCI_REG_IOBASE_U 0x30 // I/O base Upper Register
|
||||
#define PCI_REG_IOLIMIT_U 0x32 // I/O Limit Upper Register
|
||||
#define PCI_REG_INTLINE 0x3c // Interrupt Line Register
|
||||
#define PCI_REG_BRIDGE_CNTL 0x3e // Bridge Control Register
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// QuarkSCSocId Packet Hub definitions
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define PCIE_BRIDGE_VID_DID 0x88008086
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define IOH_BUS 0
|
||||
#define IOH_PCI_IOSF2AHB_0_DEV_NUM 0x14
|
||||
#define IOH_PCI_IOSF2AHB_0_MAX_FUNCS 7
|
||||
#define IOH_PCI_IOSF2AHB_1_DEV_NUM 0x15
|
||||
#define IOH_PCI_IOSF2AHB_1_MAX_FUNCS 3
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster USB definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define IOH_USB_BUS_NUMBER IOH_BUS
|
||||
#define IOH_USB_CONTROLLER_MMIO_RANGE 0x1000
|
||||
#define IOH_MAX_OHCI_USB_CONTROLLERS 1
|
||||
#define IOH_MAX_EHCI_USB_CONTROLLERS 1
|
||||
#define IOH_MAX_USBDEVICE_USB_CONTROLLERS 1
|
||||
|
||||
#define R_IOH_USB_VENDOR_ID 0x00
|
||||
#define V_IOH_USB_VENDOR_ID INTEL_VENDOR_ID
|
||||
#define R_IOH_USB_DEVICE_ID 0x02
|
||||
#define R_IOH_USB_COMMAND 0x04
|
||||
#define B_IOH_USB_COMMAND_BME BIT2
|
||||
#define B_IOH_USB_COMMAND_MSE BIT1
|
||||
#define B_IOH_USB_COMMAND_ISE BIT0
|
||||
#define R_IOH_USB_MEMBAR 0x10
|
||||
#define B_IOH_USB_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
|
||||
#define R_IOH_USB_OHCI_HCCABAR 0x18
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster OHCI definitions
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_USB_OHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_OHCI_FUNCTION_NUMBER 0x04
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster EHCI definitions
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_USB_EHCI_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_EHCI_FUNCTION_NUMBER 0x03
|
||||
|
||||
//
|
||||
// EHCI memory mapped registers offset from memory BAR0.
|
||||
//
|
||||
#define R_IOH_EHCI_CAPLENGTH 0x00
|
||||
#define R_IOH_EHCI_INSNREG01 0x94
|
||||
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP (16)
|
||||
#define B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK \
|
||||
(0xff << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
|
||||
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP (0)
|
||||
#define B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK \
|
||||
(0xff << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)
|
||||
|
||||
//
|
||||
// EHCI memory mapped registers offset from memory BAR0 + Cap length value.
|
||||
//
|
||||
#define R_IOH_EHCI_CONFIGFLAGS 0x40
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster USB Device definitions
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_USBDEVICE_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_USBDEVICE_FUNCTION_NUMBER 0x02
|
||||
|
||||
//
|
||||
// USB Device memory mapped registers offset from memory BAR0.
|
||||
//
|
||||
#define R_IOH_USBDEVICE_D_INTR_UDC_REG 0x40c
|
||||
#define R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG 0x410
|
||||
#define B_IOH_USBDEVICE_D_INTR_MSK_UDC_REG_MASK1_MASK 0xff
|
||||
#define R_IOH_USBDEVICE_EP_INTR_UDC_REG 0x414
|
||||
#define R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG 0x418
|
||||
#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK 0x000f0000
|
||||
#define B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK 0x0000000f
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster 10/100 Mbps Ethernet Device definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
#define IOH_MAC0_BUS_NUMBER IOH_BUS
|
||||
#define IOH_MAC0_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_MAC0_FUNCTION_NUMBER 0x06
|
||||
#define IOH_MAC1_BUS_NUMBER IOH_BUS
|
||||
#define IOH_MAC1_DEVICE_NUMBER IOH_PCI_IOSF2AHB_0_DEV_NUM
|
||||
#define IOH_MAC1_FUNCTION_NUMBER 0x07
|
||||
|
||||
//
|
||||
// MAC Device PCI config registers.
|
||||
//
|
||||
#define R_IOH_MAC_DEVICE_ID 0x02
|
||||
#define V_IOH_MAC_VENDOR_ID INTEL_VENDOR_ID
|
||||
#define R_IOH_MAC_DEVICE_ID 0x02
|
||||
#define V_IOH_MAC_DEVICE_ID 0x0937
|
||||
#define R_IOH_MAC_COMMAND 0x04
|
||||
#define B_IOH_MAC_COMMAND_BME BIT2
|
||||
#define B_IOH_MAC_COMMAND_MSE BIT1
|
||||
#define B_IOH_MAC_COMMAND_ISE BIT0
|
||||
#define R_IOH_MAC_MEMBAR 0x10
|
||||
#define B_IOH_MAC_MEMBAR_ADDRESS_MASK 0xFFFFF000
|
||||
|
||||
//
|
||||
// LAN Device memory mapped registers offset from memory BAR0.
|
||||
//
|
||||
#define R_IOH_MAC_GMAC_REG_8 0x20
|
||||
#define B_IOH_MAC_USERVER_MASK 0x0000FF00
|
||||
#define B_IOH_MAC_SNPSVER_MASK 0x000000FF
|
||||
#define R_IOH_MAC_GMAC_REG_16 0x40
|
||||
#define B_IOH_MAC_ADDRHI_MASK 0x0000FFFF
|
||||
#define B_IOH_MAC_AE BIT31
|
||||
#define R_IOH_MAC_GMAC_REG_17 0x44
|
||||
#define B_IOH_MAC_ADDRLO_MASK 0xFFFFFFFF
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark I2C / GPIO definitions
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID
|
||||
#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934
|
||||
|
||||
#define R_IOH_I2C_MEMBAR 0x10
|
||||
#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].
|
||||
|
||||
#define GPIO_SWPORTA_DR 0x00
|
||||
#define GPIO_SWPORTA_DDR 0x04
|
||||
#define GPIO_INTEN 0x30
|
||||
#define GPIO_INTMASK 0x34
|
||||
#define GPIO_INTTYPE_LEVEL 0x38
|
||||
#define GPIO_INT_POLARITY 0x3C
|
||||
#define GPIO_INTSTATUS 0x40
|
||||
#define GPIO_RAW_INTSTATUS 0x44
|
||||
#define GPIO_DEBOUNCE 0x48
|
||||
#define GPIO_PORTA_EOI 0x4C
|
||||
#define GPIO_EXT_PORTA 0x50
|
||||
#define GPIO_EXT_PORTB 0x54
|
||||
#define GPIO_LS_SYNC 0x60
|
||||
#define GPIO_CONFIG_REG2 0x70
|
||||
#define GPIO_CONFIG_REG1 0x74
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Quark South Cluster UART definitions.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define R_IOH_UART_MEMBAR 0x10
|
||||
#define B_IOH_UART_MEMBAR_ADDRESS_MASK 0xFFFFF000 // [31:12].
|
||||
|
||||
#endif
|
||||
|
|
@ -1,826 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
/*
|
||||
* QuarkNcSocId Register Definitions
|
||||
* Definitions beginning with "R_" are registers
|
||||
* Definitions beginning with "B_" are bits within registers
|
||||
* Definitions beginning with "V_" are meaningful values of bits within registers
|
||||
* Definitions beginning with "S_" are register sizes
|
||||
* Definitions beginning with "N_" are the bit position
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _QUARK_NC_SOC_ID_H_
|
||||
#define _QUARK_NC_SOC_ID_H_
|
||||
|
||||
//
|
||||
// Define the bits
|
||||
//
|
||||
#ifndef BIT0
|
||||
#define BIT0 0x00000001
|
||||
#define BIT1 0x00000002
|
||||
#define BIT2 0x00000004
|
||||
#define BIT3 0x00000008
|
||||
#define BIT4 0x00000010
|
||||
#define BIT5 0x00000020
|
||||
#define BIT6 0x00000040
|
||||
#define BIT7 0x00000080
|
||||
#define BIT8 0x00000100
|
||||
#define BIT9 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#endif
|
||||
|
||||
//
|
||||
// QNC GMCH Equates
|
||||
//
|
||||
|
||||
//
|
||||
// DEVICE 0 (Memory Controller Hub)
|
||||
//
|
||||
#define MC_BUS PCI_BUS_NUMBER_QNC
|
||||
#define MC_DEV 0x00
|
||||
#define MC_FUN 0x00
|
||||
|
||||
#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID
|
||||
#define QUARK_MC_DEVICE_ID 0x0958
|
||||
#define QUARK2_MC_DEVICE_ID 0x12C0
|
||||
#define QNC_MC_REV_ID_A0 0x00
|
||||
|
||||
//
|
||||
// MCR - B0:D0:F0:RD0h (WO)- Message control register (Datasheet 12.5)
|
||||
// [31:24] Message opcode - D0 read; E0 write;
|
||||
// [23:16] Message port
|
||||
// [15:8 ] Message target register address
|
||||
// [ 7:4 ] Message write byte enable : F is enable
|
||||
// [ 3:0 ] Reserved
|
||||
//
|
||||
#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register
|
||||
// Always Set to 0xF0
|
||||
#define QNC_MCR_MASK 0x000000ff
|
||||
#define QNC_MCR_BYTE_ENABLES 0x000000f0
|
||||
|
||||
//
|
||||
//MDR - B0:D0:F0:RD4h (RW)- Message data register
|
||||
//
|
||||
#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register
|
||||
|
||||
//
|
||||
//MEA - B0:D0:F0:RD8h (RW)- Message extended address register
|
||||
//
|
||||
#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Addr reg
|
||||
#define QNC_MEA_MASK 0xffffff00
|
||||
|
||||
#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR
|
||||
#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR
|
||||
#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR
|
||||
|
||||
//
|
||||
// Misc Useful Macros
|
||||
//
|
||||
|
||||
#define LShift16(value) (value << 16)
|
||||
|
||||
//
|
||||
// QNC Message OpCodes and Attributes
|
||||
//
|
||||
#define QUARK_OPCODE_READ 0x10 // Message bus "read" opcode
|
||||
#define QUARK_OPCODE_WRITE 0x11 // Message bus "write" opcode
|
||||
|
||||
//
|
||||
// Alternative opcodes for the SCSS block
|
||||
//
|
||||
#define QUARK_ALT_OPCODE_READ 0x06 // Message bus "read" opcode
|
||||
#define QUARK_ALT_OPCODE_WRITE 0x07 // Message bus "write" opcode
|
||||
|
||||
//
|
||||
// QNC Message OpCodes and Attributes for IO
|
||||
//
|
||||
#define QUARK_OPCODE_IO_READ 0x02 // Message bus "IO read" opcode
|
||||
#define QUARK_OPCODE_IO_WRITE 0x03 // Message bus "IO write" opcode
|
||||
|
||||
#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Message bus "RMU Main binary
|
||||
// shadow" opcode
|
||||
|
||||
#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark RMU "scrub resume" opcode
|
||||
#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark RMU "scrub pause" opcode
|
||||
|
||||
//
|
||||
// QNC Message Ports and Registers
|
||||
//
|
||||
// Start of SB Port IDs
|
||||
#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00
|
||||
#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01
|
||||
#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03
|
||||
#define QUARK_NC_RMU_SB_PORT_ID 0x04
|
||||
#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05
|
||||
#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14
|
||||
#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16
|
||||
#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31
|
||||
#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33
|
||||
#define QUARK_ICLK_SB_PORT_ID 0x32
|
||||
#define QUARK_SCSS_CRU_SB_PORT_ID 0x34
|
||||
|
||||
//
|
||||
// Quark Memory Arbiter Registers.
|
||||
//
|
||||
#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI
|
||||
// Status encodings reg
|
||||
#define ASTATUS_PRI_CASUAL 0x0 // Service if convenient
|
||||
#define ASTATUS_PRI_IMPENDING 0x1 // DRAM is in Self-Refresh
|
||||
#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing
|
||||
#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing
|
||||
#define ASTATUS1_RASISED_BP (10)
|
||||
#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
#define ASTATUS0_RASISED_BP (8)
|
||||
#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
#define ASTATUS1_DEFAULT_BP (2)
|
||||
#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
#define ASTATUS0_DEFAULT_BP (0)
|
||||
#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP)
|
||||
|
||||
//
|
||||
// Quark Memory Controller Registers.
|
||||
//
|
||||
#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register
|
||||
#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.
|
||||
|
||||
//
|
||||
// Quark Remote Management Unit Registers.
|
||||
//
|
||||
#define QNC_MSG_TMPM_REG_PMBA 0x70 // PM I/O Base Address
|
||||
|
||||
#define QUARK_NC_RMU_REG_CONFIG 0x71 // RMU configuration reg
|
||||
#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6)
|
||||
#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5)
|
||||
|
||||
#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // RMU Options register 1
|
||||
#define OPTIONS_1_DMA_DISABLE (BIT0)
|
||||
|
||||
#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // RMU Watchdog control
|
||||
#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)
|
||||
#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE 0
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT \
|
||||
(0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM \
|
||||
(0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR \
|
||||
(0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
|
||||
|
||||
#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // RMU Thermal sensor mode
|
||||
#define TS_ENABLE (BIT15)
|
||||
#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // RMU Thermal sensor
|
||||
// programmable trip point
|
||||
#define TS_HOT_TRIP_CLEAR_THOLD_BP 24
|
||||
#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP)
|
||||
#define TS_CAT_TRIP_CLEAR_THOLD_BP 16
|
||||
#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP)
|
||||
#define TS_HOT_TRIP_SET_THOLD_BP 8
|
||||
#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP)
|
||||
#define TS_CAT_TRIP_SET_THOLD_BP 0
|
||||
#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP)
|
||||
|
||||
#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50
|
||||
#define SCRUB_CFG_INTERVAL_SHIFT 0x00
|
||||
#define SCRUB_CFG_INTERVAL_MASK 0xFF
|
||||
#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08
|
||||
#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F
|
||||
#define SCRUB_CFG_ACTIVE (BIT13)
|
||||
#define SCRUB_CFG_INVALID 0x00000FFF
|
||||
|
||||
#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76
|
||||
#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77
|
||||
#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C
|
||||
|
||||
#define SCRUB_RESUME_MSG() ((UINT32)( \
|
||||
(QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \
|
||||
(QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
|
||||
0xF0))
|
||||
|
||||
#define SCRUB_PAUSE_MSG() ((UINT32)( \
|
||||
(QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \
|
||||
(QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \
|
||||
0xF0))
|
||||
|
||||
//
|
||||
// Quark Memory Manager Registers
|
||||
//
|
||||
#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82
|
||||
#define BLOCK_ENABLE_PG (1 << 28)
|
||||
#define BLOCK_DISABLE_PG (1 << 29)
|
||||
#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19
|
||||
#define EnableIMRInt BIT31
|
||||
#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C
|
||||
#define EnableSMMInt BIT31
|
||||
#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20
|
||||
#define DRAM_NON_HOST_RQ_LIMIT_BP 0
|
||||
#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP)
|
||||
|
||||
#define QUARK_NC_TOTAL_IMR_SET 0x8
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00
|
||||
#define IMR_LOCK BIT31
|
||||
#define IMR_EN BIT30
|
||||
#define IMRL_MASK 0x00FFFFFC
|
||||
#define IMRL_RESET 0x00000000
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01
|
||||
#define IMRH_MASK 0x00FFFFFC
|
||||
#define IMRH_RESET 0x00000000
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02
|
||||
#define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03
|
||||
#define IMRX_ALL_ACCESS 0xFFFFFFFF
|
||||
#define CPU_SNOOP BIT30
|
||||
#define RMU BIT29
|
||||
#define CPU0_NON_SMM BIT0
|
||||
|
||||
//
|
||||
// Quark Host Bridge Registers (Datasheet 12.7.2)
|
||||
//
|
||||
#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls
|
||||
#define SMI_EN (BIT19) // SMI Global Enable
|
||||
// (from Legacy Bridge)
|
||||
#define FSEG_RD_DRAM (BIT2) // Enable RAM for 0xf0000
|
||||
// - 0xfffff
|
||||
#define ESEG_RD_DRAM (BIT1) // Enable RAM for 0xe0000
|
||||
// - 0xeffff
|
||||
#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control
|
||||
#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN
|
||||
#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN
|
||||
#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN
|
||||
#define SMM_CTL_EN (BIT3) // SMM enable
|
||||
#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN
|
||||
#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN
|
||||
#define SMM_LOCKED (BIT0) // SMM Locked
|
||||
#define SMM_START_MASK 0x0000FFF0
|
||||
#define SMM_END_MASK 0xFFF00000
|
||||
#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08
|
||||
#define HMBOUND_MASK 0x0FFFFF000
|
||||
#define HMBOUND_LOCK BIT0
|
||||
#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A
|
||||
#define HLEGACY_SMI_PIN_VALUE BIT12
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54
|
||||
#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68
|
||||
#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69
|
||||
|
||||
//
|
||||
// System On Chip Unit (SOCUnit) Registers.
|
||||
//
|
||||
#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00
|
||||
#define B_STPDDRCFG_FORCE_RECOVERY BIT0
|
||||
#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25
|
||||
#define B_ROM_FUSE_IN_SECURE_SKU BIT6
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31
|
||||
#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)
|
||||
#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3
|
||||
#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9\
|
||||
| BIT8)
|
||||
#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8
|
||||
#define B_TSCGF1_CONFIG_IBGEN BIT17
|
||||
#define B_TSCGF1_CONFIG_IBGEN_BP 17
|
||||
#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18
|
||||
#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18
|
||||
#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14
|
||||
#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32
|
||||
#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF
|
||||
#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0
|
||||
#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000
|
||||
#define B_TSCGF2_CONFIG_IDSTIMING_BP 16
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33
|
||||
#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000
|
||||
#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24
|
||||
#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8)
|
||||
#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8
|
||||
#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF
|
||||
#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34
|
||||
#define B_TSCGF3_CONFIG_ITSRST BIT0
|
||||
#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11
|
||||
#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK \
|
||||
(0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP)
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36
|
||||
#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20
|
||||
#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19
|
||||
#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18
|
||||
#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17
|
||||
#define SOCCLKEN_CONFIG_BB_RST_B BIT16
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36
|
||||
|
||||
#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51
|
||||
#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0
|
||||
#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1
|
||||
#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2
|
||||
#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3
|
||||
#define B_CFG_STICKY_RW_WARM_RST BIT4
|
||||
#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9
|
||||
#define B_CFG_STICKY_RW_VIOLATION \
|
||||
(B_CFG_STICKY_RW_SMM_VIOLATION \
|
||||
| B_CFG_STICKY_RW_HMB_VIOLATION \
|
||||
| B_CFG_STICKY_RW_IMR_VIOLATION \
|
||||
| B_CFG_STICKY_RW_DECC_VIOLATION)
|
||||
#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION \
|
||||
| B_CFG_STICKY_RW_WARM_RST)
|
||||
|
||||
//
|
||||
// iCLK Registers.
|
||||
//
|
||||
#define QUARK_ICLK_MUXTOP 0x0140
|
||||
#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23)
|
||||
#define B_MUXTOP_FLEX2_BP 23
|
||||
#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20)
|
||||
#define B_MUXTOP_FLEX1_BP 20
|
||||
|
||||
#define QUARK_ICLK_SSC1 0x0314
|
||||
#define QUARK_ICLK_SSC2 0x0414
|
||||
#define QUARK_ICLK_SSC3 0x0514
|
||||
#define QUARK_ICLK_REF2_DBUFF0 0x2000
|
||||
|
||||
//
|
||||
// PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID).
|
||||
//
|
||||
#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080
|
||||
#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180
|
||||
#define OCFGPIMIXLOAD_1_0 BIT6
|
||||
#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F
|
||||
|
||||
//
|
||||
// QNC ICH Equates
|
||||
//
|
||||
#define V_INTEL_VENDOR_ID 0x8086
|
||||
|
||||
#define PCI_BUS_NUMBER_QNC 0x00
|
||||
|
||||
//
|
||||
// PCI to LPC Bridge Registers (D31:F0)
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_QNC_LPC 31
|
||||
#define PCI_FUNCTION_NUMBER_QNC_LPC 0
|
||||
|
||||
#define R_QNC_LPC_VENDOR_ID 0x00
|
||||
#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID
|
||||
#define R_QNC_LPC_DEVICE_ID 0x02
|
||||
#define QUARK_V_LPC_DEVICE_ID_0 0x095E
|
||||
#define R_QNC_LPC_REV_ID 0x08
|
||||
|
||||
#define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43
|
||||
#define B_QNC_LPC_SMBUS_BASE_EN (BIT31)
|
||||
#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6]
|
||||
//
|
||||
// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h)
|
||||
// Suggested Value for SMBA = 0x1040
|
||||
//
|
||||
#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W
|
||||
#define B_QNC_SMBUS_START (BIT4) // Start/Stop
|
||||
#define V_QNC_SMBUS_HCTL_CMD_QUICK 0
|
||||
#define V_QNC_SMBUS_HCTL_CMD_BYTE 1
|
||||
#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2
|
||||
#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3
|
||||
#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4
|
||||
#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5
|
||||
|
||||
#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W
|
||||
#define B_QNC_SMBUS_BERR (BIT2) // BUS Error
|
||||
#define B_QNC_SMBUS_DERR (BIT1) // Device Error
|
||||
#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status
|
||||
#define B_QNC_SMBUS_HSTS_ALL 0x07
|
||||
|
||||
#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W
|
||||
#define V_QNC_SMBUS_HCLK_100KHZ 0x0054
|
||||
|
||||
#define R_QNC_SMBUS_TSA 0x04 // Tx Slave Address Register R/W
|
||||
#define V_QNC_SMBUS_RW_SEL_READ 1
|
||||
#define V_QNC_SMBUS_RW_SEL_WRITE 0
|
||||
|
||||
#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W
|
||||
#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W
|
||||
#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W
|
||||
#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W
|
||||
// [255:0] ~ 3Fh
|
||||
|
||||
#define R_QNC_LPC_GBA_BASE 0x44
|
||||
#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0
|
||||
//
|
||||
// GPIO register offsets from GBA - "GPIO" (D31:F0:R44h)
|
||||
// Suggested Value for GBA = 0x1080
|
||||
//
|
||||
#define R_QNC_GPIO_CGEN_CORE_WELL 0x00
|
||||
#define R_QNC_GPIO_CGIO_CORE_WELL 0x04
|
||||
#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08
|
||||
#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // CW GPIO Trigger Pos Edge Enable
|
||||
#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // CW GPIO Trigger Neg Edge Enable
|
||||
#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable
|
||||
#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable
|
||||
#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status
|
||||
#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20
|
||||
#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24
|
||||
#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28
|
||||
#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // RW GPIO Trigger Pos Edge Enable
|
||||
#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // RW GPIO Trigger Neg Edge Enable
|
||||
#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable
|
||||
#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable
|
||||
#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status
|
||||
#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable
|
||||
#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable
|
||||
|
||||
#define R_QNC_LPC_PM1BLK 0x48
|
||||
#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0
|
||||
//
|
||||
// ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h)
|
||||
// Suggested Value for PM1BLK = 0x1000
|
||||
//
|
||||
#define R_QNC_PM1BLK_PM1S 0x00
|
||||
#define S_QNC_PM1BLK_PM1S 2
|
||||
#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)
|
||||
#define B_QNC_PM1BLK_PM1S_WAKE (BIT15)
|
||||
#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)
|
||||
#define B_QNC_PM1BLK_PM1S_RTC (BIT10)
|
||||
#define B_QNC_PM1BLK_PM1S_GLOB (BIT5)
|
||||
#define B_QNC_PM1BLK_PM1S_TO (BIT0)
|
||||
#define N_QNC_PM1BLK_PM1S_RTC 10
|
||||
|
||||
#define R_QNC_PM1BLK_PM1E 0x02
|
||||
#define S_QNC_PM1BLK_PM1E 2
|
||||
#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14)
|
||||
#define B_QNC_PM1BLK_PM1E_RTC (BIT10)
|
||||
#define B_QNC_PM1BLK_PM1E_GLOB (BIT5)
|
||||
#define N_QNC_PM1BLK_PM1E_RTC 10
|
||||
|
||||
#define R_QNC_PM1BLK_PM1C 0x04
|
||||
#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13)
|
||||
#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10)
|
||||
#define V_S0 0x00000000
|
||||
#define V_S3 0x00001400
|
||||
#define V_S4 0x00001800
|
||||
#define V_S5 0x00001C00
|
||||
#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0)
|
||||
|
||||
#define R_QNC_PM1BLK_PM1T 0x08
|
||||
|
||||
#define R_QNC_LPC_GPE0BLK 0x4C
|
||||
#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0
|
||||
// Suggested Value for GPE0BLK = 0x10C0
|
||||
//
|
||||
#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status
|
||||
#define S_QNC_GPE0BLK_GPE0S 4
|
||||
#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // Clear the status reg
|
||||
#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE
|
||||
#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO
|
||||
#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE
|
||||
#define N_QNC_GPE0BLK_GPE0S_THRM 12
|
||||
|
||||
#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable
|
||||
#define S_QNC_GPE0BLK_GPE0E 4
|
||||
#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE
|
||||
#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO
|
||||
#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE
|
||||
#define N_QNC_GPE0BLK_GPE0E_THRM 12
|
||||
|
||||
#define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable
|
||||
#define S_QNC_GPE0BLK_SMIE 4
|
||||
#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F
|
||||
#define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM
|
||||
#define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep
|
||||
#define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer
|
||||
#define N_QNC_GPE0BLK_SMIE_GPIO 9
|
||||
#define N_QNC_GPE0BLK_SMIE_ESMI 8
|
||||
#define N_QNC_GPE0BLK_SMIE_APM 4
|
||||
#define N_QNC_GPE0BLK_SMIE_SPI 3
|
||||
#define N_QNC_GPE0BLK_SMIE_SLP 2
|
||||
#define N_QNC_GPE0BLK_SMIE_SWT 1
|
||||
|
||||
#define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register.
|
||||
#define S_QNC_GPE0BLK_SMIS 4
|
||||
#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F
|
||||
#define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI
|
||||
#define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM
|
||||
#define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI
|
||||
#define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep
|
||||
#define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer
|
||||
#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS
|
||||
#define N_QNC_GPE0BLK_SMIS_GPIO 9
|
||||
#define N_QNC_GPE0BLK_SMIS_APM 4
|
||||
#define N_QNC_GPE0BLK_SMIS_SPI 3
|
||||
#define N_QNC_GPE0BLK_SMIS_SLP 2
|
||||
#define N_QNC_GPE0BLK_SMIS_SWT 1
|
||||
|
||||
#define R_QNC_GPE0BLK_PMCW 0x28 // PM Configuration Core Well
|
||||
#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable
|
||||
|
||||
#define R_QNC_GPE0BLK_PMSW 0x2C // PM Config Suspend/Resume Well
|
||||
#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Init Sctrachpad
|
||||
|
||||
#define R_QNC_LPC_ACTL 0x58
|
||||
#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00
|
||||
|
||||
//
|
||||
// Number of PIRQs supported. PIRQA~PIRQH
|
||||
//
|
||||
#define QNC_NUMBER_PIRQS 8
|
||||
#define R_QNC_LPC_PIRQA_ROUT 0x60
|
||||
#define R_QNC_LPC_PIRQB_ROUT 0x61
|
||||
#define R_QNC_LPC_PIRQC_ROUT 0x62
|
||||
#define R_QNC_LPC_PIRQD_ROUT 0x63
|
||||
#define R_QNC_LPC_PIRQE_ROUT 0x64
|
||||
#define R_QNC_LPC_PIRQF_ROUT 0x65
|
||||
#define R_QNC_LPC_PIRQG_ROUT 0x66
|
||||
#define R_QNC_LPC_PIRQH_ROUT 0x67
|
||||
|
||||
//
|
||||
// Bit values are the same for R_TNC_LPC_PIRQA_ROUT to
|
||||
// R_TNC_LPC_PIRQH_ROUT
|
||||
#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)
|
||||
|
||||
#define R_QNC_LPC_WDTBA 0x84
|
||||
// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)-------BEGIN
|
||||
#define R_QNC_LPC_WDT_WDTCR 0x10
|
||||
#define R_QNC_LPC_WDT_WDTLR 0x18
|
||||
// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)---------END
|
||||
|
||||
#define R_QNC_LPC_FWH_BIOS_DEC 0xD4
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25)
|
||||
#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24)
|
||||
|
||||
#define R_QNC_LPC_BIOS_CNTL 0xD8
|
||||
#define S_QNC_LPC_BIOS_CNTL 4
|
||||
#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8)
|
||||
#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5)
|
||||
#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2)
|
||||
#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)
|
||||
#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0)
|
||||
#define N_QNC_LPC_BIOS_CNTL_BLE 1
|
||||
#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0
|
||||
|
||||
#define R_QNC_LPC_RCBA 0xF0
|
||||
#define B_QNC_LPC_RCBA_MASK 0xFFFFC000
|
||||
#define B_QNC_LPC_RCBA_EN (BIT0)
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// Fixed IO Decode on QuarkNcSocId
|
||||
//
|
||||
// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B): R/W 8259 master
|
||||
// 30h(2B) 34h(2B) 38h(2B) 3Ch(2B): R/W 8259 master
|
||||
// 40h(3B): R/W 8254
|
||||
// 43h(1B): W 8254
|
||||
// 50h(3B): R/W 8254
|
||||
// 53h(1B): W 8254
|
||||
// 61h(1B): R/W NMI Controller
|
||||
// 63h(1B): R/W NMI Controller - can be disabled
|
||||
// 65h(1B): R/W NMI Controller - can be disabled
|
||||
// 67h(1B): R/W NMI Controller - can be disabled
|
||||
// 70h(1B): W NMI & RTC
|
||||
// 71h(1B): R/W RTC
|
||||
// 72h(1B): R RTC; W NMI&RTC
|
||||
// 73h(1B): R/W RTC
|
||||
// 74h(1B): R RTC; W NMI&RTC
|
||||
// 75h(1B): R/W RTC
|
||||
// 76h(1B): R RTC; W NMI&RTC
|
||||
// 77h(1B): R/W RTC
|
||||
// 84h(3B): R/W Internal/LPC
|
||||
// 88h(1B): R/W Internal/LPC
|
||||
// 8Ch(3B): R/W Internal/LPC
|
||||
// A0h(2B) A4h(2B) A8h(2B) ACh(2B): R/W 8259 slave
|
||||
// B0h(2B): R/W 8259 slave
|
||||
// B2h(1B) B3h(1B): R/W Power management
|
||||
// B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave
|
||||
// 3B0h-3BBh: R/W VGA
|
||||
// 3C0h-3DFh: R/W VGA
|
||||
// CF8h(4B): R/W Internal
|
||||
// CF9h(1B): R/W LPC
|
||||
// CFCh(4B): R/W Internal
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
#define R_APM_CNT 0xB2
|
||||
|
||||
//
|
||||
// Reset Generator I/O Port
|
||||
//
|
||||
#define RST_CNT 0xCF9
|
||||
#define B_RST_CNT_COLD_RST (BIT3) // Cold reset
|
||||
#define B_RST_CNT_WARM_RST (BIT1) // Warm reset
|
||||
|
||||
//
|
||||
// Processor interface registers (NMI)
|
||||
//
|
||||
|
||||
#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20
|
||||
#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21
|
||||
#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0
|
||||
|
||||
//
|
||||
// Pci Express Root Ports (D23:F0/F1)
|
||||
//
|
||||
#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23
|
||||
#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0
|
||||
#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1
|
||||
|
||||
#define MAX_PCI_EXPRESS_ROOT_PORTS 2
|
||||
|
||||
#define R_QNC_PCIE_BNUM 0x18
|
||||
#define R_QNC_PCIE_CAP_PTR 0x34
|
||||
|
||||
#define PCIE_CAPID 0x10 //PCIE Capability ID
|
||||
#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID
|
||||
#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability offset
|
||||
#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability offset
|
||||
#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset
|
||||
#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset
|
||||
#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability offset
|
||||
|
||||
#define R_QNC_PCIE_XCAP 0x42 //~ 43h
|
||||
#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented
|
||||
#define R_QNC_PCIE_DCAP 0x44 //~ 47h
|
||||
// L1 Acceptable exit latency
|
||||
#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9)
|
||||
// L0 Acceptable exit latency
|
||||
#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6)
|
||||
#define R_QNC_PCIE_DCTL 0x48 //~ 49h
|
||||
// Reporting Enables
|
||||
#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request
|
||||
#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error
|
||||
#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error
|
||||
#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error
|
||||
#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh
|
||||
#define B_QNC_PCIE_LCAP_CPM (BIT18) //clk Pwr Mgmt supported
|
||||
// Exit latency mask
|
||||
#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 ELM
|
||||
#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 ELM
|
||||
// Active state link PM support
|
||||
#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10)
|
||||
#define V_QNC_PCIE_LCAP_APMS_OFFSET 10
|
||||
#define R_QNC_PCIE_LCTL 0x50 //~ 51h
|
||||
#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock config
|
||||
#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link
|
||||
#define R_QNC_PCIE_LSTS 0x52 //~ 53h
|
||||
#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration
|
||||
#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training
|
||||
#define R_QNC_PCIE_SLCAP 0x54 //~ 57h
|
||||
#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F
|
||||
// Slot power limit value [14:7]
|
||||
#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value
|
||||
#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit offset
|
||||
// Slot number is [31:19]
|
||||
#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset
|
||||
#define R_QNC_PCIE_SLCTL 0x58 //~ 59h
|
||||
#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable
|
||||
#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable
|
||||
#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable
|
||||
#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh
|
||||
#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State
|
||||
#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed
|
||||
#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attn Button Pressed
|
||||
#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh
|
||||
// Root PCI-E Interrupt enables
|
||||
#define B_QNC_PCIE_RCTL_PIE (BIT3) // PME Interrupt Enable
|
||||
#define B_QNC_PCIE_RCTL_SFE (BIT2) // Fatal Error Enable
|
||||
#define B_QNC_PCIE_RCTL_SNE (BIT1) // Non-Fatal Error Enable
|
||||
#define B_QNC_PCIE_RCTL_SCE (BIT0) // Correctable Error Enbl
|
||||
#define R_QNC_PCIE_SVID 0x94 //~ 97h
|
||||
#define R_QNC_PCIE_CCFG 0xD0 //~ D3h
|
||||
// Upstream
|
||||
#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Posted Split Disable
|
||||
#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Non-Posted Rqstd Size
|
||||
#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Posted Request Size
|
||||
#define R_QNC_PCIE_MPC2 0xD4 //~ D7h
|
||||
#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Tx Md
|
||||
#define R_QNC_PCIE_MPC 0xD8 //~ DBh
|
||||
#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable
|
||||
#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable
|
||||
|
||||
#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable
|
||||
#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable
|
||||
#define R_QNC_PCIE_IOSFSBCTL 0xF6
|
||||
// IOSF Sideband ISM Idle Counter.
|
||||
#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0)
|
||||
// Never transition to IDLE.
|
||||
#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0)
|
||||
|
||||
#define V_PCIE_MAX_TRY_TIMES 200
|
||||
|
||||
//
|
||||
// Misc PCI register offsets and sizes
|
||||
//
|
||||
#define R_EFI_PCI_SVID 0x2C
|
||||
|
||||
//
|
||||
// IO_APIC
|
||||
//
|
||||
#define IOAPIC_BASE 0xFEC00000
|
||||
#define IOAPIC_SIZE 0x1000
|
||||
|
||||
//
|
||||
// Chipset configuration registers RCBA - "Root Complex Base Address"
|
||||
// (D31:F0:RF0h)
|
||||
// Suggested Value for RCBA = 0xFED1C000
|
||||
//
|
||||
|
||||
#define R_QNC_RCRB_SPIBASE 0x3020 // Serial Peripheral Interface in RCRB
|
||||
#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status
|
||||
#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown
|
||||
#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status
|
||||
#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status
|
||||
#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress
|
||||
|
||||
#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control
|
||||
#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable
|
||||
#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,
|
||||
// 32,40,48,56,64)
|
||||
#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer
|
||||
#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer
|
||||
#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence
|
||||
#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go
|
||||
|
||||
#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address
|
||||
#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask
|
||||
#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08)
|
||||
// SPI Data 0
|
||||
#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54)
|
||||
// Prefix Opcode Configuration
|
||||
#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56)
|
||||
// Opcode Type Configuration
|
||||
#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0
|
||||
#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)
|
||||
#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)
|
||||
#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 | BIT1)
|
||||
// Opcode Menu Configuration //R_OPMENU
|
||||
#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58)
|
||||
|
||||
// Protected BIOS Range 0 - 2
|
||||
#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60)
|
||||
#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64)
|
||||
#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68)
|
||||
// Write Protection Enable for above 3 registers.
|
||||
#define B_QNC_RCRB_SPIPBRn_WPE (BIT31)
|
||||
|
||||
#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route
|
||||
#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route
|
||||
#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route
|
||||
#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route
|
||||
|
||||
#endif
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_ACPI_H_
|
||||
#define _SOC_ACPI_H_
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <acpi/acpigen.h>
|
||||
|
||||
#endif /* _SOC_ACPI_H_ */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_CAR_H_
|
||||
#define _SOC_CAR_H_
|
||||
|
||||
#include <fsp/util.h>
|
||||
|
||||
/* Mainboard and SoC initialization prior to console. */
|
||||
void car_mainboard_pre_console_init(void);
|
||||
void car_soc_pre_console_init(void);
|
||||
|
||||
/* Mainboard and SoC initialization post console initialization. */
|
||||
void car_mainboard_post_console_init(void);
|
||||
void car_soc_post_console_init(void);
|
||||
|
||||
#endif /* _SOC_CAR_H_ */
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_CPU_H_
|
||||
#define _QUARK_CPU_H_
|
||||
|
||||
#include <device/device.h>
|
||||
|
||||
/* Supported CPUIDs */
|
||||
#define CPUID_QUARK_X1000 0x590
|
||||
|
||||
#endif /* _QUARK_CPU_H_ */
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_I2C_H_
|
||||
#define _QUARK_I2C_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct _I2C_REGS {
|
||||
volatile uint32_t ic_con; /* 00: Control Register */
|
||||
volatile uint32_t ic_tar; /* 04: Master Target Address */
|
||||
uint32_t reserved_08[2];
|
||||
volatile uint32_t ic_data_cmd; /* 10: Data Buffer & Command */
|
||||
uint32_t ic_ss_scl_hcnt; /* 14: Standard Speed Clock SCL High Count */
|
||||
uint32_t ic_ss_scl_lcnt; /* 18: Standard Speed Clock SCL Low Count */
|
||||
uint32_t ic_fs_scl_hcnt; /* 1c: Fast Speed Clock SCL High Count */
|
||||
uint32_t ic_fs_scl_lcnt; /* 20: Fast Speed Clock SCL Low Count */
|
||||
uint32_t reserved_24[2];
|
||||
volatile uint32_t ic_intr_stat; /* 2c: Interrupt Status */
|
||||
uint32_t ic_intr_mask; /* 30: Interrupt Mask */
|
||||
uint32_t ic_raw_intr_stat; /* 34: Raw Interrupt Status */
|
||||
uint32_t ic_rx_tl; /* 38: Receive FIFO Threshold Level */
|
||||
uint32_t ic_tx_tl; /* 3c: Transmit FIFO Threshold Level */
|
||||
uint32_t ic_clr_intr; /* 40: Clear Combined/Individual Interrupt */
|
||||
uint32_t ic_clr_rx_under; /* 44: Clear RX_UNDER Interrupt */
|
||||
uint32_t ic_clr_rx_over; /* 48: Clear RX_OVER Interrupt */
|
||||
uint32_t ic_clr_tx_over; /* 4c: Clear TX_OVER Interrupt */
|
||||
uint32_t ic_clr_rd_req; /* 50: Clear RD_REQ Interrupt */
|
||||
uint32_t ic_clr_tx_abrt; /* 54: Clear TX_ABRT Interrupt */
|
||||
uint32_t reserved_58;
|
||||
uint32_t ic_clr_activity; /* 5c: Clear ACTIVITY Interrupt */
|
||||
uint32_t ic_clr_stop_det; /* 60: Clear STOP_DET Interrupt */
|
||||
uint32_t ic_clr_start_det; /* 64: Clear START_DET Interrupt */
|
||||
uint32_t reserved_68;
|
||||
volatile uint32_t ic_enable; /* 6c: Enable */
|
||||
volatile uint32_t ic_status; /* 70: Status */
|
||||
uint32_t ic_txflr; /* 74: Transmit FIFO Level */
|
||||
uint32_t ic_rxflr; /* 78: Receive FIFO Level */
|
||||
uint32_t ic_sda_hold; /* 7c: SDA Hold */
|
||||
volatile uint32_t ic_tx_abrt_source; /* 80: Transmit Abort Source */
|
||||
uint32_t reserved_84[6];
|
||||
volatile uint32_t ic_enable_status; /* 9c: Enable Status */
|
||||
uint32_t ic_fs_spklen; /* a0: SS and FS Spike Suppression Limit */
|
||||
} I2C_REGS;
|
||||
|
||||
#define IC_CON offsetof(I2C_REGS, ic_con)
|
||||
#define IC_TAR offsetof(I2C_REGS, ic_tar)
|
||||
#define IC_DATA_CMD offsetof(I2C_REGS, ic_data_cmd)
|
||||
#define IC_SS_SCL_HCNT offsetof(I2C_REGS, ic_ss_scl_hcnt)
|
||||
#define IC_SS_SCL_LCNT offsetof(I2C_REGS, ic_ss_scl_lcnt)
|
||||
#define IC_FS_SCL_HCNT offsetof(I2C_REGS, ic_fs_scl_hcnt)
|
||||
#define IC_FS_SCL_LCNT offsetof(I2C_REGS, ic_fs_scl_lcnt)
|
||||
#define IC_INTR_STAT offsetof(I2C_REGS, ic_intr_stat)
|
||||
#define IC_INTR_MASK offsetof(I2C_REGS, ic_intr_mask)
|
||||
#define IC_RAW_INTR_STAT offsetof(I2C_REGS, ic_raw_intr_stat)
|
||||
#define IC_RX_TL offsetof(I2C_REGS, ic_rx_tl)
|
||||
#define IC_TX_TL offsetof(I2C_REGS, ic_tx_tl)
|
||||
#define IC_CLR_INTR offsetof(I2C_REGS, ic_clr_intr)
|
||||
#define IC_CLR_RX_UNDER offsetof(I2C_REGS, ic_clr_rx_under)
|
||||
#define IC_CLR_RX_OVER offsetof(I2C_REGS, ic_clr_rx_over)
|
||||
#define IC_CLR_TX_OVER offsetof(I2C_REGS, ic_clr_tx_over)
|
||||
#define IC_CLR_RD_REQ offsetof(I2C_REGS, ic_clr_rd_req)
|
||||
#define IC_CLR_TX_ABRT offsetof(I2C_REGS, ic_clr_tx_abrt)
|
||||
#define IC_CLR_ACTIVITY offsetof(I2C_REGS, ic_clr_activity)
|
||||
#define IC_CLR_STOP_DET offsetof(I2C_REGS, ic_clr_stop_det)
|
||||
#define IC_CLR_START_DET offsetof(I2C_REGS, ic_clr_start_det)
|
||||
#define IC_ENABLE offsetof(I2C_REGS, ic_enable)
|
||||
#define IC_STATUS offsetof(I2C_REGS, ic_status)
|
||||
#define IC_TXFLR offsetof(I2C_REGS, ic_txflr)
|
||||
#define IC_RXFLR offsetof(I2C_REGS, ic_rxflr)
|
||||
#define IC_SDA_HOLD offsetof(I2C_REGS, ic_sda_hold)
|
||||
#define IC_TX_ABRT_SOURCE offsetof(I2C_REGS, ic_tx_abrt_source)
|
||||
#define IC_ENABLE_STATUS offsetof(I2C_REGS, ic_enable_status)
|
||||
#define IC_FS_SPKLEN offsetof(I2C_REGS, ic_fs_spklen)
|
||||
|
||||
/* 0x00: ic_con */
|
||||
#define IC_CON_RESTART_EN 0x00000020 /* Enable start/restart */
|
||||
#define IC_CON_10B 0x00000010 /* 10-bit addressing */
|
||||
#define IC_CON_7B 0 /* 7-bit addressing */
|
||||
#define IC_CON_SPEED 0x00000006 /* I2C bus speed */
|
||||
#define IC_CON_SPEED_400_KHz 0x00000004 /* Fast mode */
|
||||
#define IC_CON_SPEED_100_KHz 0x00000002 /* Standard mode */
|
||||
#define IC_CON_MASTER_MODE 0x00000001 /* Enable master mode */
|
||||
|
||||
/* 0x10: ic_data_cmd */
|
||||
#define IC_DATA_CMD_RESTART 0x00000400 /* Send restart before byte */
|
||||
#define IC_DATA_CMD_STOP 0x00000200 /* Send stop after byte */
|
||||
#define IC_DATA_CMD_CMD 0x00000100 /* Type of transaction */
|
||||
#define IC_DATA_CMD_READ IC_DATA_CMD_CMD
|
||||
#define IC_DATA_CMD_WRITE 0
|
||||
#define IC_DATA_CMD_DATA 0x000000ff /* Data byte */
|
||||
|
||||
/* 0x2c: ic_intr_stat
|
||||
* 0x30: ic_intr_mask
|
||||
* 0x34: ic_raw_intr_stat
|
||||
*/
|
||||
#define IC_INTR_START_DET 0x00000400 /* Start bit detected */
|
||||
#define IC_INTR_STOP_DET 0x00000200 /* Stop bit detected */
|
||||
#define IC_INTR_ACTIVITY 0x00000100 /* Activity detected */
|
||||
#define IC_INTR_TX_ABRT 0x00000040 /* Transmit abort */
|
||||
#define IC_INTR_RD_REQ 0x00000020 /* Read request */
|
||||
#define IC_INTR_TX_EMPTY 0x00000010 /* TX FIFO is empty */
|
||||
#define IC_INTR_TX_OVER 0x00000008 /* TX FIFO overflow */
|
||||
#define IC_INTR_RX_FULL 0x00000004 /* Receive FIFO is full */
|
||||
#define IC_INTR_RX_OVER 0x00000002 /* Receive FIFO overflow */
|
||||
#define IC_INTR_RX_UNDER 0x00000001 /* Receive FIFO underflow */
|
||||
|
||||
/* 0x6c: ic_enable
|
||||
* 0x9c: ic_enable_status
|
||||
*/
|
||||
#define IC_ENABLE_CONTROLLER 0x00000001 /* Enable the I2C controller */
|
||||
|
||||
/* 0x70: ic_status */
|
||||
#define IC_STATUS_MST_ACTIVITY 0x00000020 /* Master FSM activity */
|
||||
#define IC_STATUS_RFF 0x00000010 /* Receive FIFO completely full */
|
||||
#define IC_STATUS_RFNE 0x00000008 /* Receive FIFO not empty */
|
||||
#define IC_STATUS_TFE 0x00000004 /* Transmit FIFO completely empty */
|
||||
#define IC_STATUS_TFNF 0x00000002 /* Transmit FIFO not full */
|
||||
#define IC_STATUS_ACTIVITY 0x00000001 /* Activity */
|
||||
|
||||
#endif /* _QUARK_I2C_H_ */
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_IOMAP_H_
|
||||
#define _QUARK_IOMAP_H_
|
||||
|
||||
/*
|
||||
* Memory Mapped IO base addresses.
|
||||
*/
|
||||
|
||||
/* UART MMIO */
|
||||
#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
|
||||
|
||||
/* I2C/GPIO Controller */
|
||||
#define I2C_BASE_ADDRESS 0xa0020000
|
||||
#define GPIO_BASE_ADDRESS 0xa0021000
|
||||
|
||||
/* Temporary BAR for SD controller */
|
||||
#define SD_BASE_ADDRESS 0xa0022000
|
||||
|
||||
/*
|
||||
* I/O port address space
|
||||
*/
|
||||
#define GPE0_BASE_ADDRESS 0x2000
|
||||
#define GPE0_SIZE 0x40
|
||||
|
||||
#define PM1BLK_BASE_ADDRESS 0x2040
|
||||
#define PM1BLK_SIZE 0x10
|
||||
|
||||
#define LEGACY_GPIO_BASE_ADDRESS 0x2080
|
||||
#define LEGACY_GPIO_SIZE 0x80
|
||||
|
||||
#define IO_ADDRESS_VALID 0x80000000
|
||||
|
||||
#endif /* _QUARK_IOMAP_H_ */
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef SOC_INTEL_QUARK_NVS_H
|
||||
#define SOC_INTEL_QUARK_NVS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct __packed global_nvs {
|
||||
uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
|
||||
uint8_t unused_was_pwrs; /* 0x4 - Power state (AC = 1) */
|
||||
|
||||
/* Required for future unified acpi_save_wake_source. */
|
||||
uint32_t pm1i;
|
||||
uint32_t gpei;
|
||||
};
|
||||
|
||||
#endif /* SOC_INTEL_QUARK_NVS_H */
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_PCI_DEVS_H_
|
||||
#define _QUARK_PCI_DEVS_H_
|
||||
|
||||
#include <device/pci.h>
|
||||
|
||||
/* DEVICE 0 (Memory Controller Hub) */
|
||||
#define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN)
|
||||
|
||||
/* Device IDs */
|
||||
#define I2CGPIO_DEVID 0x0934
|
||||
#define HSUART_DEVID 0x0936
|
||||
#define EHCI_DEVID 0x0939
|
||||
#define LPC_DEVID 0x095E
|
||||
#define PCIE_PORT0_DEVID 0x11c3
|
||||
#define PCIE_PORT1_DEVID 0x11c4
|
||||
|
||||
/* IO Fabric 1 */
|
||||
#define SIO1_DEV 0x14
|
||||
#define SD_MMC_DEV SIO1_DEV
|
||||
#define HSUART0_DEV SIO1_DEV
|
||||
#define HSUART1_DEV SIO1_DEV
|
||||
#define SD_MMC_FUNC 0
|
||||
#define HSUART0_FUNC 1
|
||||
#define USB_DEV_PORT_FUNC 2
|
||||
#define EHCI_FUNC 3
|
||||
#define OHCI_FUNC 4
|
||||
#define HSUART1_FUNC 5
|
||||
#define HSUART0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART0_DEV, HSUART0_FUNC)
|
||||
#define HSUART1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, HSUART1_DEV, HSUART1_FUNC)
|
||||
|
||||
/* IO Fabric 2 */
|
||||
#define SIO2_DEV 0x15
|
||||
#define I2CGPIO_DEV SIO2_DEV
|
||||
#define I2CGPIO_FUNC 2
|
||||
#define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC)
|
||||
|
||||
/* PCIe Ports */
|
||||
#define PCIE_DEV 0x17
|
||||
#define PCIE_PORT0_DEV PCIE_DEV
|
||||
#define PCIE_PORT0_FUNC 0
|
||||
#define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC)
|
||||
|
||||
#define PCIE_PORT1_DEV PCIE_DEV
|
||||
#define PCIE_PORT1_FUNC 1
|
||||
#define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC)
|
||||
|
||||
/* Platform Controller Unit */
|
||||
#define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC
|
||||
#define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC
|
||||
#define LPC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, LPC_DEV, LPC_FUNC)
|
||||
|
||||
#endif /* _QUARK_PCI_DEVS_H_ */
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
|
||||
#ifndef _PEI_WRAPPER_H_
|
||||
#define _PEI_WRAPPER_H_
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#define PEI_VERSION 22
|
||||
|
||||
#define ABI_X86 __attribute__((regparm(0)))
|
||||
|
||||
typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
|
||||
|
||||
struct pei_data {
|
||||
uint32_t pei_version;
|
||||
|
||||
int boot_mode;
|
||||
|
||||
/* Data read from flash and passed into MRC */
|
||||
const void *saved_data;
|
||||
int saved_data_size;
|
||||
|
||||
/* Disable use of saved data (can be set by mainboard) */
|
||||
int disable_saved_data;
|
||||
|
||||
/* Data from MRC that should be saved to flash */
|
||||
void *data_to_save;
|
||||
int data_to_save_size;
|
||||
} __packed;
|
||||
|
||||
#endif /* _PEI_WRAPPER_H_ */
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_PM_H_
|
||||
#define _SOC_PM_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
struct chipset_power_state {
|
||||
uint32_t prev_sleep_state;
|
||||
} __packed;
|
||||
|
||||
struct chipset_power_state *get_power_state(void);
|
||||
int fill_power_state(void);
|
||||
|
||||
/* STM Support */
|
||||
uint16_t get_pmbase(void);
|
||||
|
||||
#endif /* _SOC_PM_H_ */
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_RAMSTAGE_H_
|
||||
#define _SOC_RAMSTAGE_H_
|
||||
|
||||
#include <cpu/cpu.h>
|
||||
#include <device/device.h>
|
||||
#include <soc/QuarkNcSocId.h>
|
||||
|
||||
#include "../../chip.h"
|
||||
|
||||
void mainboard_gpio_i2c_init(struct device *dev);
|
||||
asmlinkage void chipset_teardown_car(void);
|
||||
|
||||
#endif /* _SOC_RAMSTAGE_H_ */
|
||||
|
|
@ -1,247 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_REG_ACCESS_H_
|
||||
#define _QUARK_REG_ACCESS_H_
|
||||
|
||||
#include <cpu/x86/cr.h>
|
||||
#include <fsp/util.h>
|
||||
#include <reg_script.h>
|
||||
#include <soc/IntelQNCConfig.h>
|
||||
#include <soc/Ioh.h>
|
||||
#include <soc/QuarkNcSocId.h>
|
||||
|
||||
enum {
|
||||
USB_PHY_REGS = 1,
|
||||
SOC_UNIT_REGS,
|
||||
RMU_TEMP_REGS,
|
||||
MICROSECOND_DELAY,
|
||||
LEG_GPIO_REGS,
|
||||
GPIO_REGS,
|
||||
PCIE_AFE_REGS,
|
||||
PCIE_RESET,
|
||||
GPE0_REGS,
|
||||
HOST_BRIDGE,
|
||||
CPU_CR,
|
||||
};
|
||||
|
||||
enum {
|
||||
SOC_TYPE = REG_SCRIPT_TYPE_SOC_BASE,
|
||||
/* Add additional SOC access types here*/
|
||||
};
|
||||
|
||||
#define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \
|
||||
_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \
|
||||
size_, reg_, mask_, value_, timeout_, reg_set_)
|
||||
|
||||
/* CPU CRx register access macros */
|
||||
#define REG_CPU_CR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
CPU_CR)
|
||||
#define REG_CPU_CR_READ(reg_) \
|
||||
REG_CPU_CR_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_CPU_CR_WRITE(reg_, value_) \
|
||||
REG_CPU_CR_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_CPU_CR_AND(reg_, value_) \
|
||||
REG_CPU_CR_RMW(reg_, value_, 0)
|
||||
#define REG_CPU_CR_RMW(reg_, mask_, value_) \
|
||||
REG_CPU_CR_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_CPU_CR_RXW(reg_, mask_, value_) \
|
||||
REG_CPU_CR_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_CPU_CR_OR(reg_, value_) \
|
||||
REG_CPU_CR_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_CPU_CR_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_CPU_CR_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_CPU_CR_XOR(reg_, value_) \
|
||||
REG_CPU_CR_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* GPE0 controller register access macros */
|
||||
#define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
GPE0_REGS)
|
||||
#define REG_GPE0_READ(reg_) \
|
||||
REG_GPE0_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_GPE0_WRITE(reg_, value_) \
|
||||
REG_GPE0_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_GPE0_AND(reg_, value_) \
|
||||
REG_GPE0_RMW(reg_, value_, 0)
|
||||
#define REG_GPE0_RMW(reg_, mask_, value_) \
|
||||
REG_GPE0_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_GPE0_RXW(reg_, mask_, value_) \
|
||||
REG_GPE0_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_GPE0_OR(reg_, value_) \
|
||||
REG_GPE0_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_GPE0_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_GPE0_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_GPE0_XOR(reg_, value_) \
|
||||
REG_GPE0_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* GPIO controller register access macros */
|
||||
#define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
GPIO_REGS)
|
||||
#define REG_GPIO_READ(reg_) \
|
||||
REG_GPIO_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_GPIO_WRITE(reg_, value_) \
|
||||
REG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_GPIO_AND(reg_, value_) \
|
||||
REG_GPIO_RMW(reg_, value_, 0)
|
||||
#define REG_GPIO_RMW(reg_, mask_, value_) \
|
||||
REG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_GPIO_RXW(reg_, mask_, value_) \
|
||||
REG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_GPIO_OR(reg_, value_) \
|
||||
REG_GPIO_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_GPIO_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_GPIO_XOR(reg_, value_) \
|
||||
REG_GPIO_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* Host bridge register access macros */
|
||||
#define REG_HOST_BRIDGE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
HOST_BRIDGE)
|
||||
#define REG_HOST_BRIDGE_READ(reg_) \
|
||||
REG_HOST_BRIDGE_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_HOST_BRIDGE_WRITE(reg_, value_) \
|
||||
REG_HOST_BRIDGE_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_HOST_BRIDGE_AND(reg_, value_) \
|
||||
REG_HOST_BRIDGE_RMW(reg_, value_, 0)
|
||||
#define REG_HOST_BRIDGE_RMW(reg_, mask_, value_) \
|
||||
REG_HOST_BRIDGE_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_HOST_BRIDGE_RXW(reg_, mask_, value_) \
|
||||
REG_HOST_BRIDGE_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_HOST_BRIDGE_OR(reg_, value_) \
|
||||
REG_HOST_BRIDGE_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_HOST_BRIDGE_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_HOST_BRIDGE_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_HOST_BRIDGE_XOR(reg_, value_) \
|
||||
REG_HOST_BRIDGE_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* Legacy GPIO register access macros */
|
||||
#define REG_LEG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
LEG_GPIO_REGS)
|
||||
#define REG_LEG_GPIO_READ(reg_) \
|
||||
REG_LEG_GPIO_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_LEG_GPIO_WRITE(reg_, value_) \
|
||||
REG_LEG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_LEG_GPIO_AND(reg_, value_) \
|
||||
REG_LEG_GPIO_RMW(reg_, value_, 0)
|
||||
#define REG_LEG_GPIO_RMW(reg_, mask_, value_) \
|
||||
REG_LEG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_LEG_GPIO_RXW(reg_, mask_, value_) \
|
||||
REG_LEG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_LEG_GPIO_OR(reg_, value_) \
|
||||
REG_LEG_GPIO_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_LEG_GPIO_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_LEG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_LEG_GPIO_XOR(reg_, value_) \
|
||||
REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* PCIE AFE register access macros */
|
||||
#define REG_PCIE_AFE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
PCIE_AFE_REGS)
|
||||
#define REG_PCIE_AFE_READ(reg_) \
|
||||
REG_PCIE_AFE_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_PCIE_AFE_WRITE(reg_, value_) \
|
||||
REG_PCIE_AFE_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_PCIE_AFE_AND(reg_, value_) \
|
||||
REG_PCIE_AFE_RMW(reg_, value_, 0)
|
||||
#define REG_PCIE_AFE_RMW(reg_, mask_, value_) \
|
||||
REG_PCIE_AFE_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_PCIE_AFE_RXW(reg_, mask_, value_) \
|
||||
REG_PCIE_AFE_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_PCIE_AFE_OR(reg_, value_) \
|
||||
REG_PCIE_AFE_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_PCIE_AFE_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_PCIE_AFE_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_PCIE_AFE_XOR(reg_, value_) \
|
||||
REG_PCIE_AFE_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* PCIe reset */
|
||||
#define MAINBOARD_PCIE_RESET(pin_value_) \
|
||||
SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 1, pin_value_, 0, PCIE_RESET)
|
||||
|
||||
/* RMU temperature register access macros */
|
||||
#define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
RMU_TEMP_REGS)
|
||||
#define REG_RMU_TEMP_READ(reg_) \
|
||||
REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_RMU_TEMP_WRITE(reg_, value_) \
|
||||
REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_RMU_TEMP_AND(reg_, value_) \
|
||||
REG_RMU_TEMP_RMW(reg_, value_, 0)
|
||||
#define REG_RMU_TEMP_RMW(reg_, mask_, value_) \
|
||||
REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_RMU_TEMP_RXW(reg_, mask_, value_) \
|
||||
REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_RMU_TEMP_OR(reg_, value_) \
|
||||
REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_RMU_TEMP_XOR(reg_, value_) \
|
||||
REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* Temperature sensor access macros */
|
||||
#define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
SOC_UNIT_REGS)
|
||||
#define REG_SOC_UNIT_READ(reg_) \
|
||||
REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_SOC_UNIT_WRITE(reg_, value_) \
|
||||
REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_SOC_UNIT_AND(reg_, value_) \
|
||||
REG_SOC_UNIT_RMW(reg_, value_, 0)
|
||||
#define REG_SOC_UNIT_RMW(reg_, mask_, value_) \
|
||||
REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_SOC_UNIT_RXW(reg_, mask_, value_) \
|
||||
REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_SOC_UNIT_OR(reg_, value_) \
|
||||
REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_SOC_UNIT_XOR(reg_, value_) \
|
||||
REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
/* Time delays */
|
||||
#define TIME_DELAY_USEC(value_) \
|
||||
SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, \
|
||||
MICROSECOND_DELAY)
|
||||
|
||||
/* USB register access macros */
|
||||
#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
|
||||
SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
|
||||
USB_PHY_REGS)
|
||||
#define REG_USB_READ(reg_) \
|
||||
REG_USB_ACCESS(READ, reg_, 0, 0, 0)
|
||||
#define REG_USB_WRITE(reg_, value_) \
|
||||
REG_USB_ACCESS(WRITE, reg_, 0, value_, 0)
|
||||
#define REG_USB_AND(reg_, value_) \
|
||||
REG_USB_RMW(reg_, value_, 0)
|
||||
#define REG_USB_RMW(reg_, mask_, value_) \
|
||||
REG_USB_ACCESS(RMW, reg_, mask_, value_, 0)
|
||||
#define REG_USB_RXW(reg_, mask_, value_) \
|
||||
REG_USB_ACCESS(RXW, reg_, mask_, value_, 0)
|
||||
#define REG_USB_OR(reg_, value_) \
|
||||
REG_USB_RMW(reg_, 0xffffffff, value_)
|
||||
#define REG_USB_POLL(reg_, mask_, value_, timeout_) \
|
||||
REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_)
|
||||
#define REG_USB_XOR(reg_, value_) \
|
||||
REG_USB_RXW(reg_, 0xffffffff, value_)
|
||||
|
||||
void *get_i2c_address(void);
|
||||
void mainboard_gpio_pcie_reset(uint32_t pin_value);
|
||||
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
|
||||
uint32_t mdr_read(void);
|
||||
void mdr_write(uint32_t value);
|
||||
void mea_write(uint32_t reg_address);
|
||||
uint32_t port_reg_read(uint8_t port, uint32_t offset);
|
||||
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
|
||||
uint32_t reg_host_bridge_unit_read(uint32_t reg_address);
|
||||
uint32_t reg_legacy_gpio_read(uint32_t reg_address);
|
||||
void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value);
|
||||
uint32_t reg_rmu_temp_read(uint32_t reg_address);
|
||||
|
||||
#endif /* _QUARK_REG_ACCESS_H_ */
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_ROMSTAGE_H_
|
||||
#define _QUARK_ROMSTAGE_H_
|
||||
|
||||
#include <soc/car.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
void clear_smi_and_wake_events(void);
|
||||
void disable_rom_shadow(void);
|
||||
void *locate_rmu_file(size_t *rmu_file_len);
|
||||
void report_platform_info(void);
|
||||
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
|
||||
void pcie_init(void);
|
||||
|
||||
#endif /* _QUARK_ROMSTAGE_H_ */
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _QUARK_SD_H_
|
||||
#define _QUARK_SD_H_
|
||||
|
||||
#define SD_PFA (0x14 << 11) /* B0:D20:F0 - SDIO controller */
|
||||
#define SD_CFG_BASE (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
|
||||
#define SD_CFG_CMD (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
|
||||
#define SD_CFG_ADDR (SD_CFG_BASE+0x10) /* Base address in PCI config space */
|
||||
#define SD_BASE_ADDR (0xA0018000) /* SD controller's base address */
|
||||
#define SD_HOST_CTRL (SD_BASE_ADDR+0x28) /* HOST_CTRL register */
|
||||
|
||||
#endif /* _QUARK_SD_H_ */
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __SOC_SPI_H__
|
||||
#define __SOC_SPI_H__
|
||||
|
||||
#include <spi_flash.h>
|
||||
#include <spi-generic.h>
|
||||
|
||||
#define SPISTS 0x3020 /* Status register */
|
||||
#define SPICTL 0x3022 /* Control register */
|
||||
#define SPIADDR 0x3024 /* Flash chip select and 24-bit address */
|
||||
#define SPIDATA 0x3028 /* 64-byte send/receive data buffer */
|
||||
#define SPIBBAR 0x3070 /* BIOS base address */
|
||||
#define SPIPREOP 0x3074 /* Prefix opcode table */
|
||||
#define SPITYPE 0x3076 /* Opcode type table */
|
||||
#define SPIOPMENU 0x3078 /* Opcode table */
|
||||
#define SPIPBR0 0x3080 /* Protected BIOS range */
|
||||
#define SPIPBR1 0x3084
|
||||
#define SPIPBR2 0x3088
|
||||
|
||||
struct flash_ctrlr {
|
||||
uint8_t rsvd_0x00[0x3020];/* 0x00 */
|
||||
uint16_t status; /* 0x3020: Status register */
|
||||
uint16_t control; /* 0x3022: Control register */
|
||||
uint32_t address; /* 0x3024: Chip select and 24-bit address */
|
||||
uint8_t data[64]; /* 0x3028: 64-byte send/receive data buffer */
|
||||
uint8_t rsvd_0x68[8]; /* 0x3068 */
|
||||
uint32_t bbar; /* 0x3070: BIOS base address */
|
||||
uint8_t prefix[2]; /* 0x3074: Prefix opcode table */
|
||||
uint16_t type; /* 0x3076: Opcode type table */
|
||||
uint8_t opmenu[8]; /* 0x3078: Opcode table */
|
||||
uint32_t pbr[3]; /* 0x3080: Protected BIOS range */
|
||||
};
|
||||
|
||||
/* 0x3020: SPISTS */
|
||||
#define SPISTS_CLD 0x8000 /* Lock SPI controller configuration */
|
||||
#define SPISTS_BA 0x0008 /* Access is blocked */
|
||||
#define SPISTS_CD 0x0004 /* Cycle done */
|
||||
#define SPISTS_CIP 0x0001 /* Cycle in progress */
|
||||
|
||||
/* 0x3022: SPICTL */
|
||||
#define SPICTL_SMIEN 0x8000 /* Assert SMI_B at cycle done */
|
||||
#define SPICTL_DC 0x4000 /* Cycle contains data */
|
||||
#define SPICTL_DBCNT 0x3f00 /* Data byte count - 1, 1 - 64 bytes */
|
||||
#define SPICTL_DBCNT_SHIFT 8
|
||||
#define SPICTL_COPTR 0x0070 /* Opcode menu index, 0 - 7 */
|
||||
#define SPICTL_COPTR_SHIFT 4
|
||||
#define SPICTL_SOPTR 0x0008 /* Prefix index, 0 - 1 */
|
||||
#define SPICTL_SOPTR_SHIFT 3
|
||||
#define SPICTL_ACS 0x0004 /* Atomic cycle sequence */
|
||||
#define SPICTL_CG 0x0002 /* Cycle go */
|
||||
#define SPICTL_AR 0x0001 /* Access request */
|
||||
|
||||
/* 0x3076: SPITYPE */
|
||||
#define SPITYPE_ADDRESS 0x0002 /* 3-byte address required */
|
||||
#define SPITYPE_PREFIX 0x0001 /* Prefix required, write/erase cycle */
|
||||
|
||||
/*
|
||||
* 0x3080: PBR0
|
||||
* 0x3084: PBR1
|
||||
* 0x3088: PBR2
|
||||
*/
|
||||
#define SPIPBR_WPE 0x80000000 /* Write protect enable */
|
||||
#define SPIPBR_PRL 0x00fff000 /* Protected range limit */
|
||||
#define SPIPBR_PRB_SHIFT 12
|
||||
#define SPIPBR_PRB 0x00000fff /* Protected range base */
|
||||
|
||||
struct spi_context {
|
||||
volatile struct flash_ctrlr *ctrlr;
|
||||
uint16_t control;
|
||||
uint16_t prefix;
|
||||
};
|
||||
|
||||
extern const struct spi_ctrlr spi_driver;
|
||||
|
||||
void spi_bios_base(uint32_t bios_base_address);
|
||||
void spi_controller_lock(void);
|
||||
void spi_display(volatile struct flash_ctrlr *ctrlr);
|
||||
const char *spi_opcode_name(int opcode);
|
||||
int spi_protection(uint32_t address, uint32_t length);
|
||||
|
||||
#endif /* __SOC_SPI_H__ */
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __STORAGE_TEST_H__
|
||||
#define __STORAGE_TEST_H__
|
||||
|
||||
#include <commonlib/sd_mmc_ctrlr.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <timer.h>
|
||||
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
uint32_t storage_test_init(pci_devfn_t dev, uint32_t *previous_bar,
|
||||
uint16_t *previous_command);
|
||||
void storage_test(uint32_t bar, int full_initialization);
|
||||
void storage_test_complete(pci_devfn_t dev, uint32_t previous_bar,
|
||||
uint16_t previous_command);
|
||||
#else
|
||||
uint32_t storage_test_init(struct device *dev, uint32_t *previous_bar,
|
||||
uint16_t *previous_command);
|
||||
void storage_test(uint32_t bar, int full_initialization);
|
||||
void storage_test_complete(struct device *dev, uint32_t previous_bar,
|
||||
uint16_t previous_command);
|
||||
#endif
|
||||
|
||||
/* Logging support */
|
||||
struct log_entry {
|
||||
struct mono_time time;
|
||||
struct mmc_command cmd;
|
||||
int cmd_issued;
|
||||
int ret;
|
||||
uint32_t response_entries;
|
||||
uint32_t response[4];
|
||||
};
|
||||
|
||||
#define LOG_ENTRIES 256
|
||||
|
||||
#endif /* __STORAGE_TEST_H__ */
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
static void pmc_read_resources(struct device *dev)
|
||||
{
|
||||
unsigned int index = 0;
|
||||
struct resource *res;
|
||||
|
||||
/* Get the normal PCI resources of this device. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* GPE0 */
|
||||
res = new_resource(dev, index++);
|
||||
res->base = GPE0_BASE_ADDRESS;
|
||||
res->size = GPE0_SIZE;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
/* PM1BLK */
|
||||
res = new_resource(dev, index++);
|
||||
res->base = PM1BLK_BASE_ADDRESS;
|
||||
res->size = PM1BLK_SIZE;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
/* Legacy GPIO */
|
||||
res = new_resource(dev, index++);
|
||||
res->base = LEGACY_GPIO_BASE_ADDRESS;
|
||||
res->size = LEGACY_GPIO_SIZE;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
/* Implemented just to fill FADT SCI_INT as 0. */
|
||||
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
|
||||
{
|
||||
*irq = 0;
|
||||
*gsi = 0;
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pmc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.scan_bus = scan_static_bus,
|
||||
};
|
||||
|
||||
static const struct pci_driver pmc __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = QUARK_V_LPC_DEVICE_ID_0,
|
||||
};
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/romstage.h>
|
||||
#include <cbmem.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||
{
|
||||
uintptr_t top_of_ram;
|
||||
uintptr_t top_of_low_usable_memory;
|
||||
|
||||
/* Locate the top of RAM */
|
||||
top_of_low_usable_memory = (uintptr_t)cbmem_top();
|
||||
top_of_ram = ALIGN_UP(top_of_low_usable_memory, 16 * MiB);
|
||||
|
||||
/* Cache postcar and ramstage */
|
||||
postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
|
||||
MTRR_TYPE_WRBACK);
|
||||
|
||||
/* Cache RMU area */
|
||||
postcar_frame_add_mtrr(pcf, (uintptr_t)top_of_low_usable_memory,
|
||||
0x10000, MTRR_TYPE_WRTHROUGH);
|
||||
|
||||
/* Cache ESRAM */
|
||||
postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
|
||||
|
||||
pcf->skip_common_mtrr = 1;
|
||||
/* Cache SPI flash - Write protect not supported */
|
||||
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
|
||||
}
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cbmem.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
static void nc_read_resources(struct device *dev)
|
||||
{
|
||||
int index = 0;
|
||||
|
||||
/* Read standard PCI resources. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* 0 -> 0xa0000 */
|
||||
ram_from_to(dev, index++, 0, 0xa0000);
|
||||
|
||||
/*
|
||||
* Reserve everything between A segment and 1MB:
|
||||
*
|
||||
* 0xa0000 - 0xbffff: legacy VGA
|
||||
* 0xc0000 - 0xdffff: RAM
|
||||
* 0xe0000 - 0xfffff: ROM shadow
|
||||
*/
|
||||
mmio_from_to(dev, index++, 0xa0000, 0xc0000);
|
||||
|
||||
reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
|
||||
|
||||
/* 0x100000 -> cbmem_top - cacheable and usable */
|
||||
ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
|
||||
|
||||
/* cbmem_top -> 0xc0000000 - reserved */
|
||||
reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), 0xc0000000);
|
||||
|
||||
/* 0xc0000000 -> 4GiB is mmio. */
|
||||
mmio_from_to(dev, index++, 0xc0000000, 4ull * GiB);
|
||||
}
|
||||
|
||||
static struct device_operations nc_ops = {
|
||||
.read_resources = nc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
};
|
||||
|
||||
static const struct pci_driver systemagent_driver __pci_driver = {
|
||||
.ops = &nc_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = QUARK_MC_DEVICE_ID
|
||||
};
|
||||
|
|
@ -1,478 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define __SIMPLE_DEVICE__
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <assert.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/cr.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
static uint16_t get_gpe0_address(uint32_t reg_address)
|
||||
{
|
||||
uint32_t gpe0_base_address;
|
||||
|
||||
/* Get the GPE0 base address */
|
||||
gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK);
|
||||
ASSERT(gpe0_base_address >= 0x80000000);
|
||||
gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK;
|
||||
|
||||
/* Return the GPE0 register address */
|
||||
return (uint16_t)(gpe0_base_address + reg_address);
|
||||
}
|
||||
|
||||
static uint32_t *get_gpio_address(uint32_t reg_address)
|
||||
{
|
||||
uint32_t gpio_base_address;
|
||||
|
||||
/* Get the GPIO base address */
|
||||
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1);
|
||||
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
||||
ASSERT(gpio_base_address != 0x00000000);
|
||||
|
||||
/* Return the GPIO register address */
|
||||
return (uint32_t *)(gpio_base_address + reg_address);
|
||||
}
|
||||
|
||||
void *get_i2c_address(void)
|
||||
{
|
||||
uint32_t gpio_base_address;
|
||||
|
||||
/* Get the GPIO base address */
|
||||
gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0);
|
||||
gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
||||
ASSERT(gpio_base_address != 0x00000000);
|
||||
|
||||
/* Return the GPIO register address */
|
||||
return (void *)gpio_base_address;
|
||||
}
|
||||
|
||||
static uint16_t get_legacy_gpio_address(uint32_t reg_address)
|
||||
{
|
||||
uint32_t gpio_base_address;
|
||||
|
||||
/* Get the GPIO base address */
|
||||
gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE);
|
||||
ASSERT(gpio_base_address >= 0x80000000);
|
||||
gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK;
|
||||
|
||||
/* Return the GPIO register address */
|
||||
return (uint16_t)(gpio_base_address + reg_address);
|
||||
}
|
||||
|
||||
static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
|
||||
{
|
||||
uint32_t offset;
|
||||
|
||||
/* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */
|
||||
if (index == MTRR_CAP_MSR)
|
||||
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
|
||||
else if (index == MTRR_DEF_TYPE_MSR)
|
||||
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE;
|
||||
else if (index == MTRR_FIX_64K_00000)
|
||||
offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000;
|
||||
else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000))
|
||||
offset = ((index - MTRR_FIX_16K_80000) << 1)
|
||||
+ QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000;
|
||||
else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000))
|
||||
offset = ((index - MTRR_FIX_4K_C0000) << 1)
|
||||
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
|
||||
else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7)))
|
||||
offset = (index - MTRR_PHYS_BASE(0))
|
||||
+ QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0;
|
||||
else {
|
||||
printk(BIOS_SPEW, "index: 0x%08lx\n", index);
|
||||
die("Invalid MTRR index specified!\n");
|
||||
}
|
||||
return offset;
|
||||
}
|
||||
|
||||
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
|
||||
{
|
||||
pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
|
||||
(opcode << QNC_MCR_OP_OFFSET)
|
||||
| ((uint32_t)port << QNC_MCR_PORT_OFFSET)
|
||||
| ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET)
|
||||
| QNC_MCR_BYTE_ENABLES);
|
||||
}
|
||||
|
||||
uint32_t mdr_read(void)
|
||||
{
|
||||
return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR);
|
||||
}
|
||||
|
||||
void mdr_write(uint32_t value)
|
||||
{
|
||||
pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value);
|
||||
}
|
||||
|
||||
void mea_write(uint32_t reg_address)
|
||||
{
|
||||
pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address
|
||||
& QNC_MEA_MASK);
|
||||
}
|
||||
|
||||
uint32_t port_reg_read(uint8_t port, uint32_t offset)
|
||||
{
|
||||
/* Read the port register */
|
||||
mea_write(offset);
|
||||
mcr_write(QUARK_OPCODE_READ, port, offset);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)
|
||||
{
|
||||
/* Write the port register */
|
||||
mea_write(offset);
|
||||
mdr_write(value);
|
||||
mcr_write(QUARK_OPCODE_WRITE, port, offset);
|
||||
}
|
||||
|
||||
static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the CPU CRx register */
|
||||
switch (reg_address) {
|
||||
case 0:
|
||||
return read_cr0();
|
||||
|
||||
case 4:
|
||||
return read_cr4();
|
||||
}
|
||||
die("ERROR - Unsupported CPU register!\n");
|
||||
}
|
||||
|
||||
static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value)
|
||||
{
|
||||
/* Write the CPU CRx register */
|
||||
switch (reg_address) {
|
||||
default:
|
||||
die("ERROR - Unsupported CPU register!\n");
|
||||
|
||||
case 0:
|
||||
write_cr0(value);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
write_cr4(value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uint32_t reg_gpe0_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the GPE0 register */
|
||||
return inl(get_gpe0_address(reg_address));
|
||||
}
|
||||
|
||||
static void reg_gpe0_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the GPE0 register */
|
||||
outl(value, get_gpe0_address(reg_address));
|
||||
}
|
||||
|
||||
static uint32_t reg_gpio_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the GPIO register */
|
||||
return *get_gpio_address(reg_address);
|
||||
}
|
||||
|
||||
static void reg_gpio_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the GPIO register */
|
||||
*get_gpio_address(reg_address) = value;
|
||||
}
|
||||
|
||||
uint32_t reg_host_bridge_unit_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the host bridge register */
|
||||
mea_write(reg_address);
|
||||
mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
|
||||
reg_address);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static void reg_host_bridge_unit_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the host bridge register */
|
||||
mea_write(reg_address);
|
||||
mdr_write(value);
|
||||
mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
|
||||
reg_address);
|
||||
}
|
||||
|
||||
uint32_t reg_legacy_gpio_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the legacy GPIO register */
|
||||
return inl(get_legacy_gpio_address(reg_address));
|
||||
}
|
||||
|
||||
void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the legacy GPIO register */
|
||||
outl(value, get_legacy_gpio_address(reg_address));
|
||||
}
|
||||
|
||||
static uint32_t reg_pcie_afe_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the PCIE AFE register */
|
||||
mea_write(reg_address);
|
||||
mcr_write(QUARK_OPCODE_IO_READ, QUARK_SC_PCIE_AFE_SB_PORT_ID,
|
||||
reg_address);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static void reg_pcie_afe_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the PCIE AFE register */
|
||||
mea_write(reg_address);
|
||||
mdr_write(value);
|
||||
mcr_write(QUARK_OPCODE_IO_WRITE, QUARK_SC_PCIE_AFE_SB_PORT_ID,
|
||||
reg_address);
|
||||
}
|
||||
|
||||
uint32_t reg_rmu_temp_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the RMU temperature register */
|
||||
mea_write(reg_address);
|
||||
mcr_write(QUARK_OPCODE_READ, QUARK_NC_RMU_SB_PORT_ID, reg_address);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static void reg_rmu_temp_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the RMU temperature register */
|
||||
mea_write(reg_address);
|
||||
mdr_write(value);
|
||||
mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_RMU_SB_PORT_ID, reg_address);
|
||||
}
|
||||
|
||||
static uint32_t reg_soc_unit_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the temperature sensor register */
|
||||
mea_write(reg_address);
|
||||
mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_SOC_UNIT_SB_PORT_ID,
|
||||
reg_address);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static void reg_soc_unit_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the temperature sensor register */
|
||||
mea_write(reg_address);
|
||||
mdr_write(value);
|
||||
mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SCSS_SOC_UNIT_SB_PORT_ID,
|
||||
reg_address);
|
||||
}
|
||||
|
||||
static uint32_t reg_usb_read(uint32_t reg_address)
|
||||
{
|
||||
/* Read the USB register */
|
||||
mea_write(reg_address);
|
||||
mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SC_USB_AFE_SB_PORT_ID,
|
||||
reg_address);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static void reg_usb_write(uint32_t reg_address, uint32_t value)
|
||||
{
|
||||
/* Write the USB register */
|
||||
mea_write(reg_address);
|
||||
mdr_write(value);
|
||||
mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SC_USB_AFE_SB_PORT_ID,
|
||||
reg_address);
|
||||
}
|
||||
|
||||
static uint64_t reg_read(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = ctx->step;
|
||||
uint64_t value = 0;
|
||||
|
||||
switch (step->id) {
|
||||
default:
|
||||
printk(BIOS_ERR,
|
||||
"ERROR - Unknown register set (0x%08x)!\n",
|
||||
step->id);
|
||||
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
|
||||
return 0;
|
||||
|
||||
case CPU_CR:
|
||||
ctx->display_prefix = "CPU CR";
|
||||
value = reg_cpu_cr_read(step->reg);
|
||||
break;
|
||||
|
||||
case GPE0_REGS:
|
||||
ctx->display_prefix = "GPE0";
|
||||
value = reg_gpe0_read(step->reg);
|
||||
break;
|
||||
|
||||
case GPIO_REGS:
|
||||
ctx->display_prefix = "GPIO";
|
||||
value = reg_gpio_read(step->reg);
|
||||
break;
|
||||
|
||||
case HOST_BRIDGE:
|
||||
ctx->display_prefix = "Host Bridge";
|
||||
value = reg_host_bridge_unit_read(step->reg);
|
||||
break;
|
||||
|
||||
case LEG_GPIO_REGS:
|
||||
ctx->display_prefix = "Legacy GPIO";
|
||||
value = reg_legacy_gpio_read(step->reg);
|
||||
break;
|
||||
|
||||
case PCIE_AFE_REGS:
|
||||
ctx->display_prefix = "PCIe AFE";
|
||||
value = reg_pcie_afe_read(step->reg);
|
||||
break;
|
||||
|
||||
case RMU_TEMP_REGS:
|
||||
ctx->display_prefix = "RMU TEMP";
|
||||
value = reg_rmu_temp_read(step->reg);
|
||||
break;
|
||||
|
||||
case SOC_UNIT_REGS:
|
||||
ctx->display_prefix = "SOC Unit";
|
||||
value = reg_soc_unit_read(step->reg);
|
||||
break;
|
||||
|
||||
case USB_PHY_REGS:
|
||||
ctx->display_prefix = "USB PHY";
|
||||
value = reg_usb_read(step->reg);
|
||||
break;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
static void reg_write(struct reg_script_context *ctx)
|
||||
{
|
||||
const struct reg_script *step = ctx->step;
|
||||
|
||||
switch (step->id) {
|
||||
default:
|
||||
printk(BIOS_ERR,
|
||||
"ERROR - Unknown register set (0x%08x)!\n",
|
||||
step->id);
|
||||
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
|
||||
return;
|
||||
|
||||
case CPU_CR:
|
||||
ctx->display_prefix = "CPU CR";
|
||||
reg_cpu_cr_write(step->reg, step->value);
|
||||
break;
|
||||
|
||||
case GPE0_REGS:
|
||||
ctx->display_prefix = "GPE0";
|
||||
reg_gpe0_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case GPIO_REGS:
|
||||
ctx->display_prefix = "GPIO";
|
||||
reg_gpio_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case HOST_BRIDGE:
|
||||
ctx->display_prefix = "Host Bridge";
|
||||
reg_host_bridge_unit_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case LEG_GPIO_REGS:
|
||||
ctx->display_prefix = "Legacy GPIO";
|
||||
reg_legacy_gpio_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case PCIE_AFE_REGS:
|
||||
ctx->display_prefix = "PCIe AFE";
|
||||
reg_pcie_afe_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case PCIE_RESET:
|
||||
if (ctx->display_features) {
|
||||
ctx->display_prefix = "PCIe reset";
|
||||
ctx->display_features &= ~REG_SCRIPT_DISPLAY_REGISTER;
|
||||
}
|
||||
mainboard_gpio_pcie_reset(step->value);
|
||||
break;
|
||||
|
||||
case RMU_TEMP_REGS:
|
||||
ctx->display_prefix = "RMU TEMP";
|
||||
reg_rmu_temp_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case SOC_UNIT_REGS:
|
||||
ctx->display_prefix = "SOC Unit";
|
||||
reg_soc_unit_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
|
||||
case MICROSECOND_DELAY:
|
||||
/* The actual delay is >= the requested delay */
|
||||
if (ctx->display_features) {
|
||||
/* Higher baud-rates will reduce the impact of
|
||||
* displaying this message
|
||||
*/
|
||||
printk(BIOS_INFO, "Delay %lld uSec\n", step->value);
|
||||
ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
|
||||
}
|
||||
udelay(step->value);
|
||||
break;
|
||||
|
||||
case USB_PHY_REGS:
|
||||
ctx->display_prefix = "USB PHY";
|
||||
reg_usb_write(step->reg, (uint32_t)step->value);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
msr_t soc_msr_read(unsigned int index)
|
||||
{
|
||||
uint32_t offset;
|
||||
union {
|
||||
uint64_t u64;
|
||||
msr_t msr;
|
||||
} value;
|
||||
|
||||
/* Read the low 32-bits of the register */
|
||||
offset = mtrr_index_to_host_bridge_register_offset(index);
|
||||
value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset);
|
||||
|
||||
/* For 64-bit registers, read the upper 32-bits */
|
||||
if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
|
||||
&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
|
||||
offset += 1;
|
||||
value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
|
||||
offset);
|
||||
}
|
||||
return value.msr;
|
||||
}
|
||||
|
||||
void soc_msr_write(unsigned int index, msr_t msr)
|
||||
{
|
||||
uint32_t offset;
|
||||
union {
|
||||
uint32_t u32[2];
|
||||
msr_t msr;
|
||||
} value;
|
||||
|
||||
/* Write the low 32-bits of the register */
|
||||
value.msr = msr;
|
||||
offset = mtrr_index_to_host_bridge_register_offset(index);
|
||||
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]);
|
||||
|
||||
/* For 64-bit registers, write the upper 32-bits */
|
||||
if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000)
|
||||
&& (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) {
|
||||
offset += 1;
|
||||
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset,
|
||||
value.u32[1]);
|
||||
}
|
||||
}
|
||||
|
||||
const struct reg_script_bus_entry soc_reg_script_bus_table = {
|
||||
SOC_TYPE, reg_read, reg_write
|
||||
};
|
||||
|
||||
REG_SCRIPT_BUS_ENTRY(soc_reg_script_bus_table);
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cf9_reset.h>
|
||||
#include <console/console.h>
|
||||
#include <fsp/util.h>
|
||||
|
||||
void chipset_handle_reset(uint32_t status)
|
||||
{
|
||||
/* Do a hard reset if Quark FSP ever requests a reset */
|
||||
printk(BIOS_ERR, "Unknown reset type %x\n", status);
|
||||
full_reset();
|
||||
}
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
romstage-y += car.c
|
||||
romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c
|
||||
romstage-y += fsp_params.c
|
||||
romstage-y += pcie.c
|
||||
romstage-y += report_platform.c
|
||||
romstage-y += romstage.c
|
||||
romstage-y += ../../../../cpu/intel/car/romstage.c
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <fsp/util.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
static const struct reg_script legacy_gpio_init[] = {
|
||||
/* Temporarily enable the legacy GPIO controller */
|
||||
REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
|
||||
| LEGACY_GPIO_BASE_ADDRESS),
|
||||
/* Temporarily enable the GPE controller */
|
||||
REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
|
||||
| GPE0_BASE_ADDRESS),
|
||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script i2c_gpio_controller_init[] = {
|
||||
/* Temporarily enable the GPIO controller */
|
||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
|
||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
|
||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script hsuart_init[] = {
|
||||
/* Enable the HSUART */
|
||||
REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
|
||||
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
void car_soc_pre_console_init(void)
|
||||
{
|
||||
/* Initialize the controllers */
|
||||
reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
|
||||
reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
|
||||
|
||||
/* Enable the HSUART */
|
||||
if (CONFIG(ENABLE_BUILTIN_HSUART0))
|
||||
reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
|
||||
if (CONFIG(ENABLE_BUILTIN_HSUART1))
|
||||
reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
|
||||
}
|
||||
|
||||
void car_soc_post_console_init(void)
|
||||
{
|
||||
report_platform_info();
|
||||
};
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <fsp/util.h>
|
||||
|
||||
void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd,
|
||||
const FSPM_UPD *fspm_new_upd)
|
||||
{
|
||||
const FSP_M_CONFIG *new;
|
||||
const FSP_M_CONFIG *old;
|
||||
|
||||
old = &fspm_old_upd->FspmConfig;
|
||||
new = &fspm_new_upd->FspmConfig;
|
||||
|
||||
/* Display the parameters for MemoryInit */
|
||||
printk(BIOS_SPEW, "UPD values for MemoryInit at: %p\n", new);
|
||||
fsp_display_upd_value("AddrMode", sizeof(old->AddrMode),
|
||||
old->AddrMode, new->AddrMode);
|
||||
fsp_display_upd_value("ChanMask", sizeof(old->ChanMask),
|
||||
old->ChanMask, new->ChanMask);
|
||||
fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth),
|
||||
old->ChanWidth, new->ChanWidth);
|
||||
fsp_display_upd_value("DramDensity", sizeof(old->DramDensity),
|
||||
old->DramDensity, new->DramDensity);
|
||||
fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal),
|
||||
old->DramRonVal, new->DramRonVal);
|
||||
fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal),
|
||||
old->DramRttNomVal, new->DramRttNomVal);
|
||||
fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal),
|
||||
old->DramRttWrVal, new->DramRttWrVal);
|
||||
fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed),
|
||||
old->DramSpeed, new->DramSpeed);
|
||||
fsp_display_upd_value("DramType", sizeof(old->DramType),
|
||||
old->DramType, new->DramType);
|
||||
fsp_display_upd_value("DramWidth", sizeof(old->DramWidth),
|
||||
old->DramWidth, new->DramWidth);
|
||||
fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize),
|
||||
old->EccScrubBlkSize, new->EccScrubBlkSize);
|
||||
fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval),
|
||||
old->EccScrubInterval, new->EccScrubInterval);
|
||||
fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags,
|
||||
new->Flags);
|
||||
fsp_display_upd_value("FspReservedMemoryLength",
|
||||
sizeof(old->FspReservedMemoryLength),
|
||||
old->FspReservedMemoryLength, new->FspReservedMemoryLength);
|
||||
fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask,
|
||||
new->RankMask);
|
||||
fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress),
|
||||
old->RmuBaseAddress, new->RmuBaseAddress);
|
||||
fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
|
||||
old->RmuLength, new->RmuLength);
|
||||
fsp_display_upd_value("SerialPortPollForChar",
|
||||
sizeof(old->SerialPortPollForChar),
|
||||
old->SerialPortPollForChar, new->SerialPortPollForChar);
|
||||
fsp_display_upd_value("SerialPortReadChar",
|
||||
sizeof(old->SerialPortReadChar),
|
||||
old->SerialPortReadChar, new->SerialPortReadChar);
|
||||
fsp_display_upd_value("SerialPortWriteChar",
|
||||
sizeof(old->SerialPortWriteChar),
|
||||
old->SerialPortWriteChar, new->SerialPortWriteChar);
|
||||
fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
|
||||
old->SmmTsegSize, new->SmmTsegSize);
|
||||
fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
|
||||
old->SocRdOdtVal, new->SocRdOdtVal);
|
||||
fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal),
|
||||
old->SocWrRonVal, new->SocWrRonVal);
|
||||
fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate),
|
||||
old->SocWrSlewRate, new->SocWrSlewRate);
|
||||
fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt,
|
||||
new->SrInt);
|
||||
fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp,
|
||||
new->SrTemp);
|
||||
fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL);
|
||||
fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW);
|
||||
fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS);
|
||||
fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD);
|
||||
fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR);
|
||||
}
|
||||
|
|
@ -1,146 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/romstage.h>
|
||||
#include <arch/symbols.h>
|
||||
#include <console/console.h>
|
||||
#include <cbmem.h>
|
||||
#include "../chip.h"
|
||||
#include <fsp/util.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
#include <soc/storage_test.h>
|
||||
|
||||
void mainboard_romstage_entry(void)
|
||||
{
|
||||
bool s3wake;
|
||||
|
||||
post_code(0x20);
|
||||
console_init();
|
||||
|
||||
if (CONFIG(STORAGE_TEST)) {
|
||||
uint32_t bar;
|
||||
pci_devfn_t dev;
|
||||
uint32_t previous_bar;
|
||||
uint16_t previous_command;
|
||||
|
||||
/* Enable the SD/MMC controller and run the test. Restore
|
||||
* the BAR and command registers upon completion.
|
||||
*/
|
||||
dev = PCI_DEV(0, SD_MMC_DEV, SD_MMC_FUNC);
|
||||
bar = storage_test_init(dev, &previous_bar, &previous_command);
|
||||
storage_test(bar, 1);
|
||||
storage_test_complete(dev, previous_bar, previous_command);
|
||||
}
|
||||
|
||||
/* Initialize DRAM */
|
||||
s3wake = fill_power_state() == ACPI_S3;
|
||||
fsp_memory_init(s3wake);
|
||||
|
||||
/* Disable the ROM shadow 0x000e0000 - 0x000fffff */
|
||||
disable_rom_shadow();
|
||||
|
||||
/* Initialize the PCIe bridges */
|
||||
pcie_init();
|
||||
}
|
||||
|
||||
static struct chipset_power_state power_state;
|
||||
|
||||
struct chipset_power_state *get_power_state(void)
|
||||
{
|
||||
return &power_state;
|
||||
}
|
||||
|
||||
int fill_power_state(void)
|
||||
{
|
||||
power_state.prev_sleep_state = 0;
|
||||
printk(BIOS_SPEW, "prev_sleep_state %d\n",
|
||||
power_state.prev_sleep_state);
|
||||
return power_state.prev_sleep_state;
|
||||
}
|
||||
|
||||
void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
|
||||
{
|
||||
FSPM_ARCH_UPD *aupd;
|
||||
const struct soc_intel_quark_config *config;
|
||||
void *rmu_data;
|
||||
size_t rmu_data_len;
|
||||
FSP_M_CONFIG *upd;
|
||||
|
||||
/* Clear SMI and wake events */
|
||||
clear_smi_and_wake_events();
|
||||
|
||||
/* Locate the RMU data file in flash */
|
||||
rmu_data = locate_rmu_file(&rmu_data_len);
|
||||
if (!rmu_data)
|
||||
die_with_post_code(POST_INVALID_CBFS,
|
||||
"Microcode file (rmu.bin) not found.");
|
||||
|
||||
/* Locate the configuration data from devicetree.cb */
|
||||
config = config_of_soc();
|
||||
|
||||
/* Update the architectural UPD values. */
|
||||
aupd = &fspm_upd->FspmArchUpd;
|
||||
aupd->BootLoaderTolumSize = cbmem_overhead_size();
|
||||
aupd->StackBase = (uintptr_t)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize);
|
||||
aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
|
||||
|
||||
/* Display the ESRAM layout */
|
||||
if (CONFIG(DISPLAY_ESRAM_LAYOUT)) {
|
||||
printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
|
||||
printk(BIOS_SPEW,
|
||||
"+-------------------+ 0x80080000 - ESRAM end\n");
|
||||
printk(BIOS_SPEW, "| FSP binary |\n");
|
||||
printk(BIOS_SPEW,
|
||||
"+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n",
|
||||
CONFIG_FSP_ESRAM_LOC);
|
||||
printk(BIOS_SPEW, "| FSP stack |\n");
|
||||
printk(BIOS_SPEW, "+-------------------+ 0x%zx\n",
|
||||
(size_t)aupd->StackBase);
|
||||
printk(BIOS_SPEW, "| |\n");
|
||||
printk(BIOS_SPEW, "+-------------------+ %p\n",
|
||||
_car_unallocated_start);
|
||||
printk(BIOS_SPEW, "| coreboot data |\n");
|
||||
printk(BIOS_SPEW, "+-------------------+ %p\n",
|
||||
_ecar_stack);
|
||||
printk(BIOS_SPEW, "| coreboot stack |\n");
|
||||
printk(BIOS_SPEW,
|
||||
"+-------------------+ 0x80000000 - ESRAM start\n\n");
|
||||
}
|
||||
|
||||
/* Update the UPD data for MemoryInit */
|
||||
upd = &fspm_upd->FspmConfig;
|
||||
upd->AddrMode = config->AddrMode;
|
||||
upd->ChanMask = config->ChanMask;
|
||||
upd->ChanWidth = config->ChanWidth;
|
||||
upd->DramDensity = config->DramDensity;
|
||||
upd->DramRonVal = config->DramRonVal;
|
||||
upd->DramRttNomVal = config->DramRttNomVal;
|
||||
upd->DramRttWrVal = config->DramRttWrVal;
|
||||
upd->DramSpeed = config->DramSpeed;
|
||||
upd->DramType = config->DramType;
|
||||
upd->DramWidth = config->DramWidth;
|
||||
upd->EccScrubBlkSize = config->EccScrubBlkSize;
|
||||
upd->EccScrubInterval = config->EccScrubInterval;
|
||||
upd->Flags = config->Flags;
|
||||
upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
|
||||
upd->RankMask = config->RankMask;
|
||||
upd->RmuBaseAddress = (uintptr_t)rmu_data;
|
||||
upd->RmuLength = rmu_data_len;
|
||||
upd->SerialPortWriteChar = !!console_log_level(BIOS_SPEW)
|
||||
? (uintptr_t)fsp_write_line : 0;
|
||||
upd->SmmTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
|
||||
config->SmmTsegSize : 0;
|
||||
upd->SocRdOdtVal = config->SocRdOdtVal;
|
||||
upd->SocWrRonVal = config->SocWrRonVal;
|
||||
upd->SocWrSlewRate = config->SocWrSlewRate;
|
||||
upd->SrInt = config->SrInt;
|
||||
upd->SrTemp = config->SrTemp;
|
||||
upd->tCL = config->tCL;
|
||||
upd->tFAW = config->tFAW;
|
||||
upd->tRAS = config->tRAS;
|
||||
upd->tRRD = config->tRRD;
|
||||
upd->tWTR = config->tWTR;
|
||||
}
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/reg_access.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
/* Minimum time in microseconds for assertion of PERST# signal */
|
||||
#define PCIEXP_PERST_MIN_ASSERT_US 100
|
||||
|
||||
/* Microsecond delay post issuing common lane reset */
|
||||
#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1
|
||||
|
||||
/* Microsecond delay to wait for PLL to lock */
|
||||
#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80
|
||||
|
||||
/* Microsecond delay post issuing sideband interface reset */
|
||||
#define PCIEXP_DELAY_US_POST_SBI_RESET 20
|
||||
|
||||
/* Microsecond delay post deasserting PERST# */
|
||||
#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10
|
||||
|
||||
const struct reg_script pcie_init_script[] = {
|
||||
/* Assert PCIe reset# */
|
||||
MAINBOARD_PCIE_RESET(0),
|
||||
|
||||
/* PHY Common lane reset */
|
||||
REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
|
||||
SOCCLKEN_CONFIG_PHY_I_CMNRESET_L),
|
||||
|
||||
/* Wait post common lane reset */
|
||||
TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_CMNRESET_RESET),
|
||||
|
||||
/* PHY Sideband interface reset.
|
||||
* Controller main reset
|
||||
*/
|
||||
REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
|
||||
SOCCLKEN_CONFIG_SBI_RST_100_CORE_B
|
||||
| SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L),
|
||||
TIME_DELAY_USEC(PCIEXP_DELAY_US_WAIT_PLL_LOCK),
|
||||
|
||||
/* Controller sideband interface reset */
|
||||
REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
|
||||
SOCCLKEN_CONFIG_SBI_BB_RST_B),
|
||||
|
||||
/* Wait post sideband interface reset */
|
||||
TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_SBI_RESET),
|
||||
|
||||
/* Deassert PCIe reset# */
|
||||
MAINBOARD_PCIE_RESET(1),
|
||||
|
||||
/* Wait post de assert PERST#. */
|
||||
TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_PERST_DEASSERT),
|
||||
|
||||
/* Controller primary interface reset */
|
||||
REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
|
||||
SOCCLKEN_CONFIG_BB_RST_B),
|
||||
|
||||
/* Set the mixer load resistance */
|
||||
REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0,
|
||||
OCFGPIMIXLOAD_1_0_MASK),
|
||||
REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1,
|
||||
OCFGPIMIXLOAD_1_0_MASK),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script pcie_bus_init_script[] = {
|
||||
/* Setup Message Bus Idle Counter (SBIC) values */
|
||||
REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK,
|
||||
V_PCIE_ROOT_PORT_SBIC_VALUE),
|
||||
REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL),
|
||||
|
||||
/* Set the IPF bit in MCR2 */
|
||||
REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF),
|
||||
REG_PCI_READ32(R_QNC_PCIE_MPC2),
|
||||
|
||||
/* Set up the Posted and Non Posted Request sizes for PCIe */
|
||||
REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD,
|
||||
(B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)),
|
||||
REG_PCI_READ32(R_QNC_PCIE_CCFG),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
void pcie_init(void)
|
||||
{
|
||||
/* Initialize the PCIe bridges */
|
||||
reg_script_run(pcie_init_script);
|
||||
reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script);
|
||||
reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script);
|
||||
}
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <soc/cpu.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct {
|
||||
u32 cpuid;
|
||||
u32 extended_temp;
|
||||
u32 ecc;
|
||||
u32 secure_boot;
|
||||
u32 d_variant;
|
||||
u32 mm_number;
|
||||
const char *name;
|
||||
} cpu_table[] = {
|
||||
{ CPUID_QUARK_X1000, 0, 0, 0, 0, 930237, "Quark X1000" },
|
||||
{ CPUID_QUARK_X1000, 0, 1, 0, 0, 930239, "Quark X1010" },
|
||||
{ CPUID_QUARK_X1000, 0, 1, 1, 0, 934775, "Quark X1020" },
|
||||
{ CPUID_QUARK_X1000, 0, 1, 1, 1, 930236, "Quark X1020D" },
|
||||
{ CPUID_QUARK_X1000, 1, 0, 0, 0, 934413, "Quark X1001" },
|
||||
{ CPUID_QUARK_X1000, 1, 1, 0, 0, 934415, "Quark X1011" },
|
||||
{ CPUID_QUARK_X1000, 1, 1, 1, 0, 934943, "Quark X1021" },
|
||||
{ CPUID_QUARK_X1000, 1, 1, 1, 1, 934411, "Quark X1021D" },
|
||||
};
|
||||
|
||||
static struct {
|
||||
u8 revision_id;
|
||||
const char *stepping;
|
||||
} stepping_table[] = {
|
||||
{ 0, "A0" },
|
||||
};
|
||||
|
||||
static uint32_t memory_cntrl_read(uint32_t offset)
|
||||
{
|
||||
/* Read the memory controller register */
|
||||
mea_write(offset);
|
||||
mcr_write(QUARK_OPCODE_READ, QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID,
|
||||
offset);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static uint32_t fuse_port_read(uint32_t offset)
|
||||
{
|
||||
/* Read the SoC unit register */
|
||||
mea_write(offset);
|
||||
mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_FUSE_SB_PORT_ID, offset);
|
||||
return mdr_read();
|
||||
}
|
||||
|
||||
static void report_cpu_info(void)
|
||||
{
|
||||
const char *cpu_type = "Unknown";
|
||||
u32 d_variant;
|
||||
u32 ecc_enabled;
|
||||
u32 extended_temp;
|
||||
u32 i;
|
||||
u8 revision;
|
||||
u32 secure_boot, cpu_id;
|
||||
const char *stepping = "Unknown";
|
||||
|
||||
/* Determine if ECC is enabled */
|
||||
ecc_enabled = (0 == (B_DFUSESTAT_ECC_DIS
|
||||
& memory_cntrl_read(QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT)));
|
||||
|
||||
/* Determine if secure boot is enabled */
|
||||
secure_boot = (0 != (fuse_port_read(QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE)
|
||||
& B_ROM_FUSE_IN_SECURE_SKU));
|
||||
|
||||
/* TODO: Determine if this is a D variant */
|
||||
d_variant = 0;
|
||||
if (ecc_enabled && secure_boot)
|
||||
d_variant = 0; /* or 1 */
|
||||
|
||||
/* TODO: Determine the temperature variant */
|
||||
extended_temp = 0;
|
||||
|
||||
/* Look for string to match the CPU ID value */
|
||||
cpu_id = cpu_get_cpuid();
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
|
||||
if ((cpu_table[i].cpuid == cpu_id)
|
||||
&& (cpu_table[i].extended_temp == extended_temp)
|
||||
&& (cpu_table[i].ecc == ecc_enabled)
|
||||
&& (cpu_table[i].secure_boot == secure_boot)
|
||||
&& (cpu_table[i].d_variant == d_variant)) {
|
||||
cpu_type = cpu_table[i].name;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Translate the host bridge revision ID into the stepping
|
||||
* Developer's Manual Section C.2
|
||||
*/
|
||||
revision = pci_read_config8(MC_BDF, PCI_REVISION_ID);
|
||||
for (i = 0; i < ARRAY_SIZE(stepping_table); i++) {
|
||||
if (stepping_table[i].revision_id == revision) {
|
||||
stepping = stepping_table[i].stepping;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpu_id,
|
||||
revision, cpu_type, stepping);
|
||||
}
|
||||
|
||||
void report_platform_info(void)
|
||||
{
|
||||
report_cpu_info();
|
||||
}
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <console/console.h>
|
||||
#include <fsp/util.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/reg_access.h>
|
||||
|
||||
static const struct reg_script clear_smi_and_wake_events_script[] = {
|
||||
/* Clear any SMI or wake events */
|
||||
REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S),
|
||||
REG_GPE0_READ(R_QNC_GPE0BLK_SMIS),
|
||||
REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL),
|
||||
REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
void clear_smi_and_wake_events(void)
|
||||
{
|
||||
struct chipset_power_state *ps;
|
||||
|
||||
/* Clear SMI and wake events */
|
||||
ps = get_power_state();
|
||||
if (ps->prev_sleep_state != 3) {
|
||||
printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
|
||||
reg_script_run_on_dev(LPC_BDF,
|
||||
clear_smi_and_wake_events_script);
|
||||
}
|
||||
}
|
||||
|
||||
void disable_rom_shadow(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
/* Determine if the shadow ROM is enabled */
|
||||
data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
|
||||
QNC_MSG_FSBIC_REG_HMISC);
|
||||
if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM))
|
||||
!= (ESEG_RD_DRAM | FSEG_RD_DRAM)) {
|
||||
|
||||
/* Disable the ROM shadow 0x000e0000 - 0x000fffff */
|
||||
data |= ESEG_RD_DRAM | FSEG_RD_DRAM;
|
||||
port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID,
|
||||
QNC_MSG_FSBIC_REG_HMISC, data);
|
||||
}
|
||||
}
|
||||
|
||||
void *locate_rmu_file(size_t *rmu_file_len)
|
||||
{
|
||||
size_t fsize;
|
||||
void *rmu_data;
|
||||
|
||||
/* Locate the rmu.bin file in the read-only region of the flash */
|
||||
rmu_data = cbfs_ro_map("rmu.bin", &fsize);
|
||||
if (!rmu_data)
|
||||
return NULL;
|
||||
|
||||
if (rmu_file_len != NULL)
|
||||
*rmu_file_len = fsize;
|
||||
|
||||
return rmu_data;
|
||||
}
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <commonlib/sdhci.h>
|
||||
#include <commonlib/storage.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/storage_test.h>
|
||||
|
||||
static void init(struct device *dev)
|
||||
{
|
||||
/* Run the SD test */
|
||||
if (CONFIG(STORAGE_TEST)) {
|
||||
uint32_t bar;
|
||||
uint32_t previous_bar;
|
||||
uint16_t previous_command;
|
||||
|
||||
bar = storage_test_init(dev, &previous_bar, &previous_command);
|
||||
storage_test(bar, 0);
|
||||
storage_test_complete(dev, previous_bar, previous_command);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct device_operations device_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = init,
|
||||
};
|
||||
|
||||
static const struct pci_driver pmc __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = 0x08A7,
|
||||
};
|
||||
|
|
@ -1,290 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <bootstate.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <delay.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/QuarkNcSocId.h>
|
||||
#include <soc/spi.h>
|
||||
#include <string.h>
|
||||
|
||||
struct spi_context spi_driver_context = {
|
||||
NULL,
|
||||
0,
|
||||
0
|
||||
};
|
||||
|
||||
void spi_bios_base(uint32_t bios_base_address)
|
||||
{
|
||||
uint32_t address;
|
||||
volatile struct flash_ctrlr *ctrlr = spi_driver_context.ctrlr;
|
||||
|
||||
/* Prevent all SPI operations below this address */
|
||||
address = 0xff000000 | bios_base_address;
|
||||
ctrlr->bbar = address;
|
||||
}
|
||||
|
||||
void spi_controller_lock(void)
|
||||
{
|
||||
volatile struct flash_ctrlr *ctrlr = spi_driver_context.ctrlr;
|
||||
|
||||
/* Prevent BIOS and system from changing the SPI controller setup */
|
||||
ctrlr->status |= SPISTS_CLD;
|
||||
}
|
||||
|
||||
int spi_protection(uint32_t address, uint32_t length)
|
||||
{
|
||||
uint32_t base;
|
||||
volatile struct flash_ctrlr *ctrlr = spi_driver_context.ctrlr;
|
||||
int index;
|
||||
uint32_t limit;
|
||||
uint32_t protect;
|
||||
uint32_t value;
|
||||
|
||||
/* Determine the protection range */
|
||||
base = address;
|
||||
limit = address + length - 1;
|
||||
protect = SPIPBR_WPE | (limit & SPIPBR_PRL)
|
||||
| ((base >> SPIPBR_PRB_SHIFT) & SPIPBR_PRB);
|
||||
|
||||
/* Walk the list of protected areas */
|
||||
for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
|
||||
value = read32(&ctrlr->pbr[index]);
|
||||
|
||||
/* Don't duplicate if the range is already protected */
|
||||
if (value == protect)
|
||||
return 0;
|
||||
|
||||
/* Use the first free register to protect this range */
|
||||
if ((value & SPIPBR_WPE) == 0) {
|
||||
write32(&ctrlr->pbr[index], protect);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* No free protection range registers */
|
||||
printk(BIOS_ERR,
|
||||
"Failed to set protection: 0x%08x - 0x%08x, PRRs full!\n",
|
||||
address, address + length - 1);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int xfer(const struct spi_slave *slave, const void *dout,
|
||||
size_t bytesout, void *din, size_t bytesin)
|
||||
{
|
||||
struct spi_context *context;
|
||||
uint16_t control;
|
||||
volatile struct flash_ctrlr *ctrlr;
|
||||
uint8_t *data;
|
||||
int index;
|
||||
uint8_t opcode;
|
||||
uint32_t status;
|
||||
int type;
|
||||
|
||||
/* Locate the context structure */
|
||||
context = &spi_driver_context;
|
||||
ctrlr = context->ctrlr;
|
||||
|
||||
/* Validate the buffer sizes */
|
||||
if (bytesin > sizeof(ctrlr->data)) {
|
||||
printk(BIOS_ERR, "bytesin > %zu\n", sizeof(ctrlr->data));
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (bytesin && (din == NULL)) {
|
||||
printk(BIOS_ERR, "din is NULL\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (bytesout == 0) {
|
||||
/* Check for a read operation */
|
||||
if (bytesin == 0) {
|
||||
printk(BIOS_ERR, "bytesout and bytesin == 0\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* Issue the read operation */
|
||||
control = context->control;
|
||||
control |= SPICTL_DC | ((bytesin - 1) << SPICTL_DBCNT_SHIFT);
|
||||
goto start_cycle;
|
||||
}
|
||||
|
||||
/* Locate the opcode in the opcode table */
|
||||
data = (uint8_t *)dout;
|
||||
opcode = *data++;
|
||||
bytesout -= 1;
|
||||
for (index = 0; index < sizeof(ctrlr->opmenu); index++)
|
||||
if (opcode == ctrlr->opmenu[index])
|
||||
break;
|
||||
|
||||
/* Check for a prefix byte */
|
||||
if (index == sizeof(ctrlr->opmenu)) {
|
||||
for (index = 0; index < sizeof(ctrlr->prefix); index++)
|
||||
if (opcode == ctrlr->prefix[index])
|
||||
break;
|
||||
|
||||
/* Handle the unknown opcode error */
|
||||
if (index == sizeof(ctrlr->prefix)) {
|
||||
printk(BIOS_ERR, "Unknown SPI flash opcode\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* Save the index for the next operation */
|
||||
context->prefix = index;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get the opcode type */
|
||||
type = (ctrlr->type >> (index * 2))
|
||||
& (SPITYPE_ADDRESS | SPITYPE_PREFIX);
|
||||
|
||||
/* Determine if the opcode has an address */
|
||||
if (type & SPITYPE_ADDRESS) {
|
||||
if (bytesout < 3) {
|
||||
printk(BIOS_ERR, "Missing address bytes\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* Use chip select 0 */
|
||||
ctrlr->address = (data[0] << 16)
|
||||
| (data[1] << 8)
|
||||
| data[2];
|
||||
|
||||
/* read in order to flush the write buffer */
|
||||
status = ctrlr->address;
|
||||
|
||||
data += 3;
|
||||
bytesout -= 3;
|
||||
}
|
||||
|
||||
/* Build the control value */
|
||||
control = (index << SPICTL_COPTR_SHIFT)
|
||||
| (context->prefix << SPICTL_SOPTR_SHIFT)
|
||||
| SPICTL_CG | SPICTL_AR;
|
||||
if (bytesout) {
|
||||
memcpy((void *)&ctrlr->data[0], data, bytesout);
|
||||
control |= SPICTL_DC | ((bytesout - 1) << SPICTL_DBCNT_SHIFT);
|
||||
}
|
||||
|
||||
/* Save the control value for the read operation request */
|
||||
if (!(type & SPITYPE_PREFIX)) {
|
||||
context->control = control;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Write operations require a prefix */
|
||||
control |= SPICTL_ACS;
|
||||
|
||||
start_cycle:
|
||||
/* Start the SPI cycle */
|
||||
ctrlr->control = control;
|
||||
status = ctrlr->control;
|
||||
context->prefix = 0;
|
||||
|
||||
/* Wait for the access to complete */
|
||||
while ((status = ctrlr->status) & SPISTS_CIP)
|
||||
udelay(1);
|
||||
|
||||
/* Clear any errors */
|
||||
ctrlr->status = status;
|
||||
|
||||
/* Handle the blocked access error */
|
||||
if (status & SPISTS_BA) {
|
||||
printk(BIOS_ERR, "SPI access blocked!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for done */
|
||||
if (status & SPISTS_CD) {
|
||||
/* Return any receive data */
|
||||
if (bytesin)
|
||||
memcpy(din, (void *)&ctrlr->data[0], bytesin);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Handle the timeout error */
|
||||
printk(BIOS_ERR, "SPI transaction timeout!\n");
|
||||
|
||||
error:
|
||||
context->prefix = 0;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void spi_init(void)
|
||||
{
|
||||
uint32_t bios_control;
|
||||
struct spi_context *context;
|
||||
volatile struct flash_ctrlr *ctrlr;
|
||||
struct device *dev;
|
||||
uint32_t rcba;
|
||||
|
||||
/* Determine the base address of the SPI flash controller */
|
||||
context = &spi_driver_context;
|
||||
dev = dev_find_device(PCI_VID_INTEL, LPC_DEVID, NULL);
|
||||
rcba = pci_read_config32(dev, R_QNC_LPC_RCBA);
|
||||
if (!(rcba & B_QNC_LPC_RCBA_EN)) {
|
||||
printk(BIOS_ERR, "RBCA not enabled\n");
|
||||
return;
|
||||
}
|
||||
rcba &= B_QNC_LPC_RCBA_MASK;
|
||||
ctrlr = (volatile struct flash_ctrlr *)rcba;
|
||||
|
||||
/* Enable writes to the SPI flash */
|
||||
bios_control = pci_read_config32(dev, R_QNC_LPC_BIOS_CNTL);
|
||||
bios_control |= B_QNC_LPC_BIOS_CNTL_BIOSWE;
|
||||
pci_write_config32(dev, R_QNC_LPC_BIOS_CNTL, bios_control);
|
||||
|
||||
/* Setup the SPI flash controller */
|
||||
context->ctrlr = ctrlr;
|
||||
ctrlr->opmenu[0] = 0x03; /* Read */
|
||||
ctrlr->opmenu[1] = 0x0b; /* Read fast */
|
||||
ctrlr->opmenu[2] = 0x05; /* Read status */
|
||||
ctrlr->opmenu[3] = 0x9f; /* Read ID */
|
||||
ctrlr->opmenu[4] = 0x02; /* Page program */
|
||||
ctrlr->opmenu[5] = 0x20; /* Erase 4 KiB */
|
||||
ctrlr->opmenu[6] = 0xd8; /* Erase 64 KiB */
|
||||
ctrlr->opmenu[7] = 0x01; /* Write status */
|
||||
ctrlr->prefix[0] = 0x50; /* Write status enable */
|
||||
ctrlr->prefix[1] = 0x06; /* Write enable */
|
||||
ctrlr->type = SPITYPE_ADDRESS /* Read */
|
||||
| (SPITYPE_ADDRESS << 2) /* Read fast */
|
||||
| (0 << 4) /* Read status */
|
||||
| (0 << 6) /* Read ID */
|
||||
| ((SPITYPE_ADDRESS | SPITYPE_PREFIX) << 8) /* Page program */
|
||||
| ((SPITYPE_ADDRESS | SPITYPE_PREFIX) << 10) /* Erase 4 KiB */
|
||||
| ((SPITYPE_ADDRESS | SPITYPE_PREFIX) << 12) /* Erase 64 KiB */
|
||||
| (SPITYPE_PREFIX << 14); /* Write status */
|
||||
}
|
||||
|
||||
static void spi_init_cb(void *unused)
|
||||
{
|
||||
struct spi_flash flash;
|
||||
|
||||
spi_init();
|
||||
if (spi_flash_probe(0, 0, &flash)) {
|
||||
printk(BIOS_DEBUG, "SPI flash failed initialization!\n");
|
||||
return;
|
||||
}
|
||||
printk(BIOS_DEBUG, "SPI flash successfully initialized\n");
|
||||
}
|
||||
|
||||
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
|
||||
|
||||
const struct spi_ctrlr spi_driver = {
|
||||
.xfer = xfer,
|
||||
.max_xfer_size = 64,
|
||||
};
|
||||
|
||||
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
|
||||
{
|
||||
.ctrlr = &spi_driver,
|
||||
.bus_start = 0,
|
||||
.bus_end = 0,
|
||||
},
|
||||
};
|
||||
|
||||
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <soc/spi.h>
|
||||
|
||||
const char *spi_opcode_name(int opcode)
|
||||
{
|
||||
const char *op_name;
|
||||
|
||||
switch (opcode) {
|
||||
default:
|
||||
op_name = "Unknown";
|
||||
break;
|
||||
case 1:
|
||||
op_name = "Write Status";
|
||||
break;
|
||||
case 2:
|
||||
op_name = "Page Program";
|
||||
break;
|
||||
case 3:
|
||||
op_name = "Read Data";
|
||||
break;
|
||||
case 5:
|
||||
op_name = "Read Status";
|
||||
break;
|
||||
case 6:
|
||||
op_name = "Write Data Enable";
|
||||
break;
|
||||
case 0x0b:
|
||||
op_name = "Fast Read";
|
||||
break;
|
||||
case 0x20:
|
||||
op_name = "Erase 4 KiB";
|
||||
break;
|
||||
case 0x50:
|
||||
op_name = "Write Status Enable";
|
||||
break;
|
||||
case 0x9f:
|
||||
op_name = "Read ID";
|
||||
break;
|
||||
case 0xd8:
|
||||
op_name = "Erase 64 KiB";
|
||||
break;
|
||||
}
|
||||
return op_name;
|
||||
}
|
||||
|
||||
void spi_display(volatile struct flash_ctrlr *ctrlr)
|
||||
{
|
||||
int index;
|
||||
int opcode;
|
||||
const char *op_name;
|
||||
int prefix;
|
||||
int status;
|
||||
int type;
|
||||
|
||||
/* Display the prefixes */
|
||||
printk(BIOS_DEBUG, "Prefix Table\n");
|
||||
for (index = 0; index < 2; index++) {
|
||||
prefix = ctrlr->prefix[index];
|
||||
op_name = spi_opcode_name(prefix);
|
||||
printk(BIOS_DEBUG, " %d: 0x%02x (%s)\n", index, prefix,
|
||||
op_name);
|
||||
}
|
||||
|
||||
/* Display the opcodes */
|
||||
printk(BIOS_DEBUG, "Opcode Menu\n");
|
||||
for (index = 0; index < 8; index++) {
|
||||
opcode = ctrlr->opmenu[index];
|
||||
type = (ctrlr->type >> (index << 1)) & 3;
|
||||
op_name = spi_opcode_name(opcode);
|
||||
printk(BIOS_DEBUG, " %d: 0x%02x (%s), %s%s\n", index, opcode,
|
||||
op_name,
|
||||
(type & SPITYPE_PREFIX) ? "Write" : "Read",
|
||||
(type & SPITYPE_ADDRESS) ? ", w/3 byte address" : "");
|
||||
}
|
||||
|
||||
/* Display the BIOS base address */
|
||||
printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
|
||||
|
||||
/* Display the protection ranges */
|
||||
printk(BIOS_DEBUG, "BIOS Protected Range Registers\n");
|
||||
for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
|
||||
status = ctrlr->pbr[index];
|
||||
printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n",
|
||||
index, status,
|
||||
0xff000000 | (0x1000000 - CONFIG_ROM_SIZE)
|
||||
| ((status & SPIPBR_PRB) << SPIPBR_PRB_SHIFT),
|
||||
0xff800fff | (0x1000000 - CONFIG_ROM_SIZE)
|
||||
| (status & SPIPBR_PRL),
|
||||
(status & SPIPBR_WPE) ? "Protected" : "Unprotected");
|
||||
}
|
||||
|
||||
/* Display locked status */
|
||||
status = ctrlr->status;
|
||||
printk(BIOS_DEBUG, "0x%04x: SPISTS, Tables %s\n", status,
|
||||
(status & SPISTS_CLD) ? "Locked" : "Unlocked");
|
||||
}
|
||||
|
|
@ -1,244 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <assert.h>
|
||||
#include <cbmem.h>
|
||||
#include <commonlib/sdhci.h>
|
||||
#include <commonlib/storage.h>
|
||||
#include <console/console.h>
|
||||
#include <lib.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/storage_test.h>
|
||||
#include <timer.h>
|
||||
#include <string.h>
|
||||
|
||||
#if CONFIG(STORAGE_LOG)
|
||||
struct log_entry log[LOG_ENTRIES];
|
||||
uint8_t log_index;
|
||||
int log_full;
|
||||
long log_start_time;
|
||||
#endif
|
||||
|
||||
static uint8_t drivers_storage[256];
|
||||
|
||||
#define STORAGE_DEBUG BIOS_DEBUG
|
||||
#define LOG_DEBUG (CONFIG(STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER)
|
||||
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
uint32_t storage_test_init(pci_devfn_t dev, uint32_t *previous_bar,
|
||||
uint16_t *previous_command)
|
||||
#else
|
||||
uint32_t storage_test_init(struct device *dev, uint32_t *previous_bar,
|
||||
uint16_t *previous_command)
|
||||
#endif
|
||||
{
|
||||
uint32_t bar;
|
||||
|
||||
/* Display the vendor/device IDs */
|
||||
printk(LOG_DEBUG, "Vendor ID: 0x%04x, Device ID: 0x%04x\n",
|
||||
pci_read_config16(dev, PCI_VENDOR_ID),
|
||||
pci_read_config16(dev, PCI_DEVICE_ID));
|
||||
|
||||
/* Set the temporary base address */
|
||||
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
*previous_bar = bar;
|
||||
bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
|
||||
if (!bar) {
|
||||
bar = SD_BASE_ADDRESS;
|
||||
pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar);
|
||||
}
|
||||
|
||||
/* Enable the SD/MMC controller */
|
||||
*previous_command = pci_read_config16(dev, PCI_COMMAND);
|
||||
pci_write_config16(dev, PCI_COMMAND, *previous_command
|
||||
| PCI_COMMAND_MEMORY);
|
||||
|
||||
/* Return the controller address */
|
||||
return bar;
|
||||
}
|
||||
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
void storage_test_complete(pci_devfn_t dev, uint32_t previous_bar,
|
||||
uint16_t previous_command)
|
||||
#else
|
||||
void storage_test_complete(struct device *dev, uint32_t previous_bar,
|
||||
uint16_t previous_command)
|
||||
#endif
|
||||
{
|
||||
pci_write_config16(dev, PCI_COMMAND, previous_command);
|
||||
pci_write_config32(dev, PCI_BASE_ADDRESS_0, previous_bar);
|
||||
}
|
||||
|
||||
#if !ENV_BOOTBLOCK
|
||||
static void display_log(void)
|
||||
{
|
||||
/* Determine the array bounds */
|
||||
if (CONFIG(STORAGE_LOG)) {
|
||||
long delta;
|
||||
uint8_t end;
|
||||
uint8_t index;
|
||||
uint8_t start;
|
||||
|
||||
end = log_index;
|
||||
start = log_full ? log_index : 0;
|
||||
for (index = start; (log_full || (index != end)); index++) {
|
||||
log_full = 0;
|
||||
delta = log[index].time.microseconds - log_start_time;
|
||||
printk(BIOS_DEBUG, "%3ld.%03ld mSec, cmd: %2d 0x%08x%s",
|
||||
delta / 1000, delta % 1000,
|
||||
log[index].cmd.cmdidx,
|
||||
log[index].cmd.cmdarg,
|
||||
log[index].cmd_issued ? "" : "(not issued)");
|
||||
if (log[index].response_entries == 1)
|
||||
printk(BIOS_DEBUG, ", rsp: 0x%08x",
|
||||
log[index].response[0]);
|
||||
else if (log[index].response_entries == 4)
|
||||
printk(BIOS_DEBUG,
|
||||
", rsp: 0x%08x.%08x.%08x.%08x",
|
||||
log[index].response[3],
|
||||
log[index].response[2],
|
||||
log[index].response[1],
|
||||
log[index].response[0]);
|
||||
printk(BIOS_DEBUG, ", ret: %d\n", log[index].ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void sdhc_log_command(struct mmc_command *cmd)
|
||||
{
|
||||
if (CONFIG(STORAGE_LOG)) {
|
||||
timer_monotonic_get(&log[log_index].time);
|
||||
log[log_index].cmd = *cmd;
|
||||
log[log_index].cmd_issued = 0;
|
||||
log[log_index].response_entries = 0;
|
||||
if ((log_index == 0) && (!log_full))
|
||||
log_start_time = log[0].time.microseconds;
|
||||
}
|
||||
}
|
||||
|
||||
void sdhc_log_command_issued(void)
|
||||
{
|
||||
if (CONFIG(STORAGE_LOG)) {
|
||||
log[log_index].cmd_issued = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void sdhc_log_response(uint32_t entries, uint32_t *response)
|
||||
{
|
||||
unsigned int entry;
|
||||
|
||||
if (CONFIG(STORAGE_LOG)) {
|
||||
log[log_index].response_entries = entries;
|
||||
for (entry = 0; entry < entries; entry++)
|
||||
log[log_index].response[entry] = response[entry];
|
||||
}
|
||||
}
|
||||
|
||||
void sdhc_log_ret(int ret)
|
||||
{
|
||||
if (CONFIG(STORAGE_LOG)) {
|
||||
log[log_index].ret = ret;
|
||||
if (++log_index == 0)
|
||||
log_full = 1;
|
||||
}
|
||||
}
|
||||
|
||||
void storage_test(uint32_t bar, int full_initialization)
|
||||
{
|
||||
uint64_t blocks_read;
|
||||
uint8_t buffer[512];
|
||||
int err;
|
||||
struct storage_media *media;
|
||||
const char *name;
|
||||
unsigned int partition;
|
||||
unsigned int previous_partition;
|
||||
struct sdhci_ctrlr *sdhci_ctrlr;
|
||||
|
||||
ASSERT(sizeof(struct sdhci_ctrlr) <= sizeof(drivers_storage));
|
||||
|
||||
/* Get the structure addresses */
|
||||
media = NULL;
|
||||
if (ENV_CREATES_CBMEM)
|
||||
media = (struct storage_media *)drivers_storage;
|
||||
else
|
||||
media = cbmem_find(CBMEM_ID_STORAGE_DATA);
|
||||
sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7);
|
||||
media->ctrlr = (struct sd_mmc_ctrlr *)sdhci_ctrlr;
|
||||
sdhci_ctrlr->ioaddr = (void *)bar;
|
||||
|
||||
/* Initialize the controller */
|
||||
if (!full_initialization) {
|
||||
/* Perform fast initialization */
|
||||
sdhci_update_pointers(sdhci_ctrlr);
|
||||
sdhci_display_setup(sdhci_ctrlr);
|
||||
storage_display_setup(media);
|
||||
} else {
|
||||
/* Initialize the log */
|
||||
if (CONFIG(STORAGE_LOG)) {
|
||||
log_index = 0;
|
||||
log_full = 0;
|
||||
}
|
||||
|
||||
printk(LOG_DEBUG, "Initializing the SD/MMC controller\n");
|
||||
err = sdhci_controller_init(sdhci_ctrlr, (void *)bar);
|
||||
if (err) {
|
||||
display_log();
|
||||
printk(BIOS_ERR, "Controller failed to initialize, err = %d\n",
|
||||
err);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Initialize the SD/MMC/eMMC card or device */
|
||||
printk(LOG_DEBUG, "Initializing the device\n");
|
||||
err = storage_setup_media(media, &sdhci_ctrlr->sd_mmc_ctrlr);
|
||||
if (err) {
|
||||
display_log();
|
||||
printk(BIOS_ERR, "Device failed to initialize, err = %d\n",
|
||||
err);
|
||||
return;
|
||||
}
|
||||
display_log();
|
||||
}
|
||||
|
||||
/* Save the current partition */
|
||||
previous_partition = storage_get_current_partition(media);
|
||||
|
||||
/* Read block 0 from each partition */
|
||||
for (partition = 0; partition < ARRAY_SIZE(media->capacity);
|
||||
partition++) {
|
||||
if (media->capacity[partition] == 0)
|
||||
continue;
|
||||
name = storage_partition_name(media, partition);
|
||||
printk(STORAGE_DEBUG, "%s%sReading block 0\n", name,
|
||||
name[0] ? ": " : "");
|
||||
err = storage_set_partition(media, partition);
|
||||
if (err)
|
||||
continue;
|
||||
blocks_read = storage_block_read(media, 0, 1, &buffer);
|
||||
if (blocks_read)
|
||||
hexdump(buffer, sizeof(buffer));
|
||||
}
|
||||
|
||||
/* Restore the previous partition */
|
||||
storage_set_partition(media, previous_partition);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void copy_storage_structures(int is_recovery)
|
||||
{
|
||||
struct storage_media *media;
|
||||
struct sdhci_ctrlr *sdhci_ctrlr;
|
||||
size_t size = sizeof(drivers_storage);
|
||||
|
||||
/* Locate the data structures in CBMEM */
|
||||
media = cbmem_add(CBMEM_ID_STORAGE_DATA, size);
|
||||
ASSERT(media != NULL);
|
||||
sdhci_ctrlr = (void *)(((uintptr_t)(media + 1) + 0x7) & ~7);
|
||||
|
||||
/* Migrate the data into CBMEM */
|
||||
memcpy(media, drivers_storage, size);
|
||||
media->ctrlr = &sdhci_ctrlr->sd_mmc_ctrlr;
|
||||
}
|
||||
|
||||
CBMEM_CREATION_HOOK(copy_storage_structures);
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cpu/x86/tsc.h>
|
||||
|
||||
unsigned long tsc_freq_mhz(void)
|
||||
{
|
||||
/* CPU freq = 400 MHz */
|
||||
return 400;
|
||||
}
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/uart.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <soc/pci_devs.h>
|
||||
|
||||
static void uart_read_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
/* Read the resources */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Set the debug port configuration */
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
res->base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
|
||||
res->size = 0x100;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = uart_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
};
|
||||
|
||||
static const struct pci_driver uart_driver __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VID_INTEL,
|
||||
.device = HSUART_DEVID,
|
||||
};
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/uart.h>
|
||||
#include <soc/iomap.h>
|
||||
|
||||
unsigned int uart_platform_refclk(void)
|
||||
{
|
||||
return 44236800;
|
||||
}
|
||||
|
||||
uintptr_t uart_platform_base(unsigned int idx)
|
||||
{
|
||||
return UART_BASE_ADDRESS;
|
||||
}
|
||||
Loading…
Reference in New Issue