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Documentation: gpio: Fix table 

This patch fixes the indentation issue introduced with commit 0c1c2dec
(Documentation: Capture anomalies between pad and lock reset type).

BUG=b:211573253, b:211950520

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib6974cda26e6f7968688a2a7c30c7351d212a780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2022-01-14 12:23:24 +05:30
parent 415eadb90b
commit 5338a16b2e
1 changed files with 26 additions and 53 deletions
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79
Documentation/getting_started/gpio.md
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@ -167,59 +167,32 @@ could cause catastrophic failures, up to and including your mainboard!
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as: supports four different types of GPIO reset as:
+------------------------+----------------+-------------+-------------+ | PAD Reset Config | Platform Reset | GPP | GPD |
| | | PAD Reset ? | |-------------------------------------------------|----------------|-----|-----|
+ PAD Reset Config + Platform Reset +-------------+-------------+ | 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N |
| | | GPP | GPD | | | Cold Reset | N | N |
+------------------------+----------------+-------------+-------------+ | | S3/S4/S5 | N | N |
| 00 - Power Good | Warm Reset | N | N | | | Global Reset | N | N |
| (GPP: RSMRST, +----------------+-------------+-------------+ | | Deep Sx | Y | N |
| GPD: DSW_PWROK) | Cold Reset | N | N | | | G3 | Y | N |
| +----------------+-------------+-------------+ | 01 - Deep | Warm Reset | Y | Y |
| | S3/S4/S5 | N | N | | | Cold Reset | Y | Y |
| +----------------+-------------+-------------+ | | S3/S4/S5 | N | N |
| | Global Reset | N | N | | | Global Reset | Y | Y |
| +----------------+-------------+-------------+ | | Deep Sx | Y | Y |
| | Deep Sx | Y | N | | | G3 | Y | Y |
| +----------------+-------------+-------------+ | 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| | G3 | Y | Y | | | Cold Reset | Y | Y |
+------------------------+----------------+-------------+-------------+ | | S3/S4/S5 | Y | Y |
| 01 - Deep | Warm Reset | Y | Y | | | Global Reset | Y | Y |
| +----------------+-------------+-------------+ | | Deep Sx | Y | Y |
| | Cold Reset | Y | Y | | | G3 | Y | Y |
| +----------------+-------------+-------------+ | 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N |
| | S3/S4/S5 | N | N | | | Cold Reset | - | N |
| +----------------+-------------+-------------+ | | S3/S4/S5 | - | N |
| | Global Reset | Y | Y | | | Global Reset | - | N |
| +----------------+-------------+-------------+ | | Deep Sx | - | Y |
| | Deep Sx | Y | Y | | | G3 | - | Y |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| +----------------+-------------+-------------+
| | Cold Reset | Y | Y |
| +----------------+-------------+-------------+
| | S3/S4/S5 | Y | Y |
| +----------------+-------------+-------------+
| | Global Reset | Y | Y |
| +----------------+-------------+-------------+
| | Deep Sx | Y | Y |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| 11 - Resume Reset | Warm Reset | - | N |
| (GPP: Reserved, +----------------+-------------+-------------+
| GPD: RSMRST) | Cold Reset | - | N |
| +----------------+-------------+-------------+
| | S3/S4/S5 | - | N |
| +----------------+-------------+-------------+
| | Global Reset | - | N |
| +----------------+-------------+-------------+
| | Deep Sx | - | Y |
| +----------------+-------------+-------------+
| | G3 | - | Y |
+------------------------+----------------+-------------+-------------+
Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
specific register fields in the PAD configuration register. specific register fields in the PAD configuration register.