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mb/google/poppy/variants/nautilus: enable digitizer pen device 

- Add pen device property into devicetree.cb.
- Set GPP_C9 to 0 as default.

BUG=none
BRANCH=master
TEST=emerge-nautilus coreboot and check pen device operation
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f
Reviewed-on: https://review.coreboot.org/23010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Seunghwan Kim 2017-12-28 10:40:35 +09:00 committed by Furquan Shaikh
parent ca966f9a2d
commit 533ea7adb5
2 changed files with 15 additions and 2 deletions
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15
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
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@ -308,7 +308,20 @@ chip soc/intel/skylake
end end
end # I2C #1 end # I2C #1
device pci 15.2 on end # I2C #2 device pci 15.2 on end # I2C #2
device pci 15.3 on end # I2C #3 device pci 15.3 on
chip drivers/i2c/hid
register "generic.hid" = ""ACPI0C50""
register "generic.cid" = ""PNP0C50""
register "generic.desc" = ""Digitizer device""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C9)"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "generic.wake" = "GPE0_DW0_21"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x9 on end
end
end # I2C #3
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R

2
src/mainboard/google/poppy/variants/nautilus/gpio.c
View File

@ -130,7 +130,7 @@ static const struct pad_config gpio_table[] = {
/* C8 : UART0_RXD ==> NC */ /* C8 : UART0_RXD ==> NC */
PAD_CFG_NC(GPP_C8), PAD_CFG_NC(GPP_C8),
/* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */
PAD_CFG_GPO(GPP_C9, 1, DEEP), PAD_CFG_GPO(GPP_C9, 0, DEEP),
/* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */ /* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */
PAD_CFG_GPO(GPP_C10, 1, DEEP), PAD_CFG_GPO(GPP_C10, 1, DEEP),
/* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_CAM_EN */ /* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_CAM_EN */