mb/prodrive/atlas: Add new mainboard based on adlrvp

This is a initial mainboard code cloned from adlrvp aimed to serve as
base for further mainboard check-ins. This commit copies the mainboard
directory and adjusts the naming to match the new board's name.
Besides, This commit also trims down major parts of adlrvp code except
some of ADL-P DDR5 RVP as Atlas is using it as main reference.

Follow-up commits will introduce the needed changes for the new
mainboard.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/prodrive/atlas/Kconfig

@@ -0,0 +1,32 @@
+config BOARD_PRODRIVE_ATLAS_BASEBOARD
+	def_bool n
+	select BOARD_ROMSIZE_KB_32768
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
+	select SOC_INTEL_ALDERLAKE_PCH_P
+
+if BOARD_PRODRIVE_ATLAS_BASEBOARD
+
+config MAINBOARD_FAMILY
+	string
+	default "PRODRIVE_ATLAS_SERIES"
+
+config MAINBOARD_PART_NUMBER
+	default "Atlas ADL-P"
+
+config MAINBOARD_DIR
+	default "prodrive/atlas"
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+	string
+	default "Prodrive Technologies B.V."
+
+config DIMM_SPD_SIZE
+	default 512
+
+config UART_FOR_CONSOLE
+	int
+	default 0
+
+endif #BOARD_PRODRIVE_ATLAS_BASEBOARD

src/mainboard/prodrive/atlas/Kconfig.name

@@ -0,0 +1,3 @@
+config BOARD_PRODRIVE_ATLAS
+	bool "Atlas"
+	select BOARD_PRODRIVE_ATLAS_BASEBOARD

src/mainboard/prodrive/atlas/Makefile.inc

@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += early_gpio.c
+
+romstage-y += romstage_fsp_params.c
+
+ramstage-y += gpio.c
+ramstage-y += mainboard.c

src/mainboard/prodrive/atlas/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Prodrive
+Board name: Atlas
+Category: misc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/prodrive/atlas/bootblock.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+
+#include "gpio.h"
+
+void bootblock_mainboard_early_init(void)
+{
+	configure_early_gpio_pads();
+}

src/mainboard/prodrive/atlas/devicetree.cb

@@ -0,0 +1,51 @@
+chip soc/intel/alderlake
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# Enable HECI1 interface
+	register "HeciEnabled" = "1"
+
+	device domain 0 on
+		device ref pcie5 on end
+		device ref igpu on end
+		device ref dtt on end
+		device ref pcie4_0 on end
+		device ref pcie4_1 on end
+		device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp1 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
+		device ref crashlog off end
+		device ref tcss_xhci on end
+		device ref tcss_dma0 on end
+		device ref tcss_dma1 on end
+		device ref xhci on end
+		device ref cnvi_wifi on end
+		device ref i2c0 on end
+		device ref i2c1 on end
+		device ref i2c2 on end
+		device ref i2c3 on end
+		device ref heci1 on end
+		device ref sata on end
+		device ref i2c5 on end
+		device ref pcie_rp1 on end
+		device ref pcie_rp3 on end # W/A to FSP issue
+		device ref pcie_rp4 on end # W/A to FSP issue
+		device ref pcie_rp5 on end
+		device ref pcie_rp6 on end
+		device ref pcie_rp8 on end
+		device ref pcie_rp9 on end
+		device ref pcie_rp11 on end
+		device ref uart0 on end
+		device ref gspi0 on end
+		device ref p2sb on end
+		device ref hda on end
+		device ref smbus on end
+	end
+end

src/mainboard/prodrive/atlas/dsdt.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}

src/mainboard/prodrive/atlas/early_gpio.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+
+#include "gpio.h"
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* todo: gpio config */
+};
+
+static const struct pad_config early_uart_gpio_table[] = {
+	/* todo: gpio config */
+};
+
+void configure_early_gpio_pads(void)
+{
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/prodrive/atlas/gpio.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <types.h>
+
+#include "gpio.h"
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+	/* Todo: gpio config */
+};
+
+void configure_gpio_pads(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/prodrive/atlas/gpio.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+void configure_gpio_pads(void);
+void configure_early_gpio_pads(void);
+
+#endif /* __BASEBOARD_GPIO_H__ */

src/mainboard/prodrive/atlas/mainboard.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <stdint.h>
+
+#include "gpio.h"
+
+static void mainboard_init(void *chip_info)
+{
+	configure_gpio_pads();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};

src/mainboard/prodrive/atlas/romstage_fsp_params.c

@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistor */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = { 50, 30, 30, 30, 27 },
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	}
+};
+
+void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
+{
+	const struct mb_cfg *mem_config = &ddr5_mem_config;
+	const bool half_populated = false;
+
+	const struct mem_spd dimm_module_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+				.addr_dimm[1] = 0x51,
+			},
+			[1] = {
+				.addr_dimm[0] = 0x52,
+				.addr_dimm[1] = 0x53,
+			},
+		},
+	};
+
+	memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated);
+}