tegra132, tegra210: Fix "becasue" typo in comments

This renames "becasue" occurrences to "because".

Change-Id: I7862ce6a865cb1525ca1cef69c2eb1e90cc76a9d
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14735
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Paul Kocialkowski 2016-05-07 14:31:35 +02:00 committed by Stefan Reinauer
parent 30554c8416
commit 536f5a7eb9
2 changed files with 2 additions and 2 deletions

View File

@ -138,7 +138,7 @@ void update_display_shift_clock_divider(struct display_controller *disp_ctrl,
* set up window registers and activate window except two: * set up window registers and activate window except two:
* frame buffer base address register (WINBUF_START_ADDR) and * frame buffer base address register (WINBUF_START_ADDR) and
* display enable register (_DISP_DISP_WIN_OPTIONS). This is * display enable register (_DISP_DISP_WIN_OPTIONS). This is
* becasue framebuffer is not available until payload stage. * because framebuffer is not available until payload stage.
*/ */
void update_window(const struct soc_nvidia_tegra132_config *config) void update_window(const struct soc_nvidia_tegra132_config *config)
{ {

View File

@ -138,7 +138,7 @@ void update_display_shift_clock_divider(struct display_controller *disp_ctrl,
* set up window registers and activate window except two: * set up window registers and activate window except two:
* frame buffer base address register (WINBUF_START_ADDR) and * frame buffer base address register (WINBUF_START_ADDR) and
* display enable register (_DISP_DISP_WIN_OPTIONS). This is * display enable register (_DISP_DISP_WIN_OPTIONS). This is
* becasue framebuffer is not available until payload stage. * because framebuffer is not available until payload stage.
*/ */
void update_window(const struct soc_nvidia_tegra210_config *config) void update_window(const struct soc_nvidia_tegra210_config *config)
{ {