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src/.../Kconfig: various small fixes to texts 

Fixed spelling and added empty lines to separate the help
from the text automatically added during make menuconfig.

Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6313
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Daniele Forsi 2014-07-22 18:00:56 +02:00 committed by Patrick Georgi
parent e34a6275ee
commit 53847a211b
10 changed files with 30 additions and 21 deletions
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10
src/Kconfig
View File

@ -124,7 +124,7 @@ config INCLUDE_CONFIG_FILE
in the (CBFS) ROM image. This is useful if you want to know which
options were used to build a specific coreboot.rom image.
Saying Y here will increase the image size by 2-3kB.
Saying Y here will increase the image size by 2-3KB.
You can use the following command to easily list the options:
@ -143,7 +143,7 @@ config INCLUDE_CONFIG_FILE
Name Offset Type Size
cmos_layout.bin 0x0 cmos layout 1159
fallback/romstage 0x4c0 stage 339756
fallback/ramstage 0x53440 stage 186664
fallback/ramstage 0x53440 stage 186664
fallback/payload 0x80dc0 payload 51526
config 0x8d740 raw 3324
(empty) 0x8e480 null 3610440
@ -395,7 +395,7 @@ config RELOCATABLE_MODULES
default n
help
If RELOCATABLE_MODULES is selected then support is enabled for
building relocatable modules in the ram stage. Those modules can be
building relocatable modules in the RAM stage. Those modules can be
loaded anywhere and all the relocations are handled automatically.
config RELOCATABLE_RAMSTAGE
@ -602,6 +602,7 @@ config SEABIOS_MASTER
bool "master"
help
Newest SeaBIOS version
endchoice
config SEABIOS_PS2_TIMEOUT
@ -634,6 +635,7 @@ config GRUB2_MASTER
bool "HEAD"
help
Newest GRUB2 version
endchoice
choice
@ -645,10 +647,12 @@ config FILO_STABLE
bool "0.6.0"
help
Stable FILO version
config FILO_MASTER
bool "HEAD"
help
Newest FILO version
endchoice
config PAYLOAD_FILE

4
src/console/Kconfig
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@ -147,7 +147,7 @@ config CONSOLE_NE2K_DST_IP
string "Destination IP of logging system"
default "10.0.1.27"
help
This is IP adress of the system running for example
This is IP address of the system running for example
netcat command to dump the packets.
config CONSOLE_NE2K_SRC_IP
@ -336,7 +336,7 @@ config POST_IO_PORT
default 0x80
help
POST codes on x86 are typically written to the LPC bus on port
0x80. However, it may be desireable to change the port number
0x80. However, it may be desirable to change the port number
depending on the presence of coprocessors/microcontrollers or if the
platform does not support IO in the conventional x86 manner.

6
src/cpu/amd/agesa/Kconfig
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@ -46,10 +46,10 @@ config XIP_ROM_SIZE
default 0x100000
help
Overwride the default write through caching size as 1M Bytes.
On some AMD paltform, one socket support 2 or more kinds of
processor family, compiling several cpu families agesa code
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash rom,
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.
config UDELAY_LAPIC_FIXED_FSB

4
src/cpu/x86/Kconfig
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@ -126,7 +126,7 @@ config PARALLEL_MP
config BACKUP_DEFAULT_SMM_REGION
def_bool n
help
The cpu support will select this option if the default SMM region
The CPU support will select this option if the default SMM region
needs to be backed up for suspend/resume purposes.
config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
@ -135,5 +135,5 @@ config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
On certain platforms a boot speed gain can be realized if mirroring
the payload data stored in non-volatile storage. On x86 systems the
payload would typically live in a memory-mapped SPI part. Copying
the SPI contents to ram before performing the load can speed up
the SPI contents to RAM before performing the load can speed up
the boot process.

12
src/device/Kconfig
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@ -74,11 +74,11 @@ config ALWAYS_LOAD_OPROM
def_bool n
depends on VGA_ROM_RUN
help
Always load option roms if any are found. The decision to run
the rom is still determined at runtime, but the distinction
Always load option ROMs if any are found. The decision to run
the ROM is still determined at runtime, but the distinction
between loading and not running comes into play for CHROMEOS.
An example where this is required is that VBT (video bios tables)
An example where this is required is that VBT (Video BIOS Tables)
are needed for the kernel's display driver to know how a piece of
hardware is configured to be used.
@ -493,9 +493,12 @@ config BOOTSPLASH
bool
depends on FRAMEBUFFER_SET_VESA_MODE
help
This option shows a graphical bootsplash screen. The grapics are
This option shows a graphical bootsplash screen. The graphics are
loaded from the CBFS file bootsplash.jpg.
You will be able to specify the location and file name of the
image later.
config BOOTSPLASH_FILE
string "Bootsplash path and filename"
depends on BOOTSPLASH
@ -503,6 +506,7 @@ config BOOTSPLASH_FILE
help
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
endmenu
menu "PXE ROM"

2
src/ec/kontron/it8516e/Kconfig
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@ -2,7 +2,7 @@ config EC_KONTRON_IT8516E
select EC_ACPI
bool
help
Kontron uses an ITE IT8516E on the KTQM77. It's firmware might
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
come from Fintek (mentioned as Finte*c* somewhere in their Linux
driver).
The KTQM77 is an embedded board and the IT8516E seems to be

4
src/northbridge/intel/fsp_sandybridge/Kconfig
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@ -33,8 +33,8 @@ config VGA_BIOS_ID
default "8086,0106"
help
This is the default PCI ID for the sandybridge/ivybridge graphics
devices. This string names the vbios rom in cbfs. The following
PCI IDs will be remapped to load this rom:
devices. This string names the vbios ROM in cbfs. The following
PCI IDs will be remapped to load this ROM:
0x80860102, 0x8086010a, 0x80860112, 0x80860116
0x80860122, 0x80860126, 0x80860166

2
src/soc/intel/baytrail/Kconfig
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@ -148,7 +148,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
default 0x800
help
The amount of anticipated stack usage from the data cache
during pre-ram rom stage execution.
during pre-RAM ROM stage execution.
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."

2
src/soc/intel/fsp_baytrail/Kconfig
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@ -78,7 +78,7 @@ config VGA_BIOS_ID
default "8086,0f31"
help
This is the default PCI ID for the Bay Trail graphics
devices. This string names the vbios rom in cbfs.
devices. This string names the vbios ROM in cbfs.
config INCLUDE_MICROCODE_IN_BUILD
bool "Build in microcode patch"

5
src/southbridge/amd/agesa/hudson/Kconfig
View File

@ -98,7 +98,7 @@ config HUDSON_FWM
if HUDSON_FWM
config HUDSON_FWM_POSITION
hex "Hudson Firmware rom Position"
hex "Hudson Firmware ROM Position"
default 0xFFF20000 if BOARD_ROMSIZE_KB_1024
default 0xFFE20000 if BOARD_ROMSIZE_KB_2048
default 0xFFC20000 if BOARD_ROMSIZE_KB_4096
@ -160,6 +160,7 @@ config HUDSON_SATA_IDE2AHCI7804
bool "IDE to AHCI7804"
help
AHCI ROM Required, and AMD driver required in the OS.
endchoice
config HUDSON_SATA_MODE
@ -212,7 +213,7 @@ config RAID_MISC_ROM_POSITION
help
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.
The CONFIG_ROM_SIZE must be larger than 0x100000.
endif # HUDSON_SATA_RAID
config HUDSON_LEGACY_FREE