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mb/siemens/mc_ehl1: Enable In Band ECC 

Enable IBECC for mc_ehl1 to provide a memory failure protection.

Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh 2021-07-23 11:00:17 +02:00 committed by Patrick Georgi
parent 2a174f16d9
commit 5384da40b2
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@ -20,6 +20,12 @@ chip soc/intel/elkhartlake
register "SmbusEnable" = "1" register "SmbusEnable" = "1"
register "Heci2Enable" = "1" register "Heci2Enable" = "1"
# Enable IBECC for the complete memory
register "ibecc" = "{
.enable = 1,
.mode = IBECC_ALL
}"
# USB related UPDs # USB related UPDs
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2