GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rush: Add support for chromeos_ec 

BUG=chrome-os-partner:31032
BRANCH=None
TEST=Compiles successfully and ec error fixed while booting.

Change-Id: I7bb78b8986931407ee67f33e83b9d887bea7ac70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5447adb964276b9e13399ac93140ae763a149aad
Original-Change-Id: I02172a30863b7b97892289e880c29f2d71220fda
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210436
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8898
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2014-07-29 18:47:16 -07:00 committed by Patrick Georgi
parent 472e0393eb
commit 538caba152
3 changed files with 17 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/rush/Kconfig
View File

@ -23,6 +23,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select BOARD_ID_SUPPORT select BOARD_ID_SUPPORT
select CHROMEOS select CHROMEOS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select EC_SOFTWARE_SYNC
select SPI_FLASH
select SOC_NVIDIA_TEGRA132 select SOC_NVIDIA_TEGRA132
select MAINBOARD_HAS_BOOTBLOCK_INIT select MAINBOARD_HAS_BOOTBLOCK_INIT
select VIRTUAL_DEV_SWITCH select VIRTUAL_DEV_SWITCH
@ -87,4 +91,8 @@ config DRIVER_TPM_I2C_ADDR
hex hex
default 0x20 default 0x20
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 1
endif # BOARD_GOOGLE_RUSH endif # BOARD_GOOGLE_RUSH

2
src/mainboard/google/rush/Makefile.inc
View File

@ -35,9 +35,7 @@ romstage-y += reset.c
romstage-y += romstage.c romstage-y += romstage.c
romstage-y += sdram_configs.c romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += ec_dummy.c
ramstage-y += boardid.c ramstage-y += boardid.c
ramstage-y += mainboard.c ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += ec_dummy.c

9
src/mainboard/google/rush/mainboard.c
View File

@ -23,6 +23,7 @@
#include <soc/clock.h> #include <soc/clock.h>
#include <soc/nvidia/tegra132/gpio.h> #include <soc/nvidia/tegra132/gpio.h>
#include <soc/nvidia/tegra132/clk_rst.h> #include <soc/nvidia/tegra132/clk_rst.h>
#include <soc/nvidia/tegra132/spi.h>
#include <soc/addressmap.h> #include <soc/addressmap.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -84,11 +85,19 @@ static void init_mmc(void)
} }
static void setup_ec_spi(void)
{
struct tegra_spi_channel *spi;
spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
}
static void mainboard_init(device_t dev) static void mainboard_init(device_t dev)
{ {
clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0); clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0);
init_mmc(); init_mmc();
setup_ec_spi();
} }
static void mainboard_enable(device_t dev) static void mainboard_enable(device_t dev)