soc/intel/skylake: Rename pch_init() code

This patch renames pch_init function to bootblock_pch_init and
romstage_pch_init according to the stage it is defined in.

TEST=Able to build and boot soraka successfully.

Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Usha P 2019-12-23 13:21:36 +05:30 committed by Patrick Georgi
parent f96c638a60
commit 5395123b84
6 changed files with 8 additions and 8 deletions

View File

@ -44,6 +44,6 @@ void bootblock_soc_init(void)
* and abase, i2c programming and print platform info
*/
report_platform_info();
pch_init();
bootblock_pch_init();
gspi_early_bar_init();
}

View File

@ -146,7 +146,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc();
}
void pch_init(void)
void bootblock_pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,

View File

@ -24,7 +24,7 @@ void bootblock_pch_early_init(void);
/* Bootblock post console init programming */
void i2c_early_init(void);
void pch_init(void);
void bootblock_pch_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
void report_memory_config(void);

View File

@ -21,7 +21,7 @@
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
void pch_init(void);
void romstage_pch_init(void);
int smbus_read_byte(unsigned int device, unsigned int address);
/* Board type */
enum board_type {

View File

@ -17,11 +17,11 @@
#include <intelblocks/tco.h>
#include <soc/romstage.h>
void pch_init(void)
void romstage_pch_init(void)
{
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
/* Program TCO_BASE_ADDRESS and TCO Timer Halt */
tco_configure();
/* Program SMBUS_BASE_ADDRESS and Enable it */
/* Program SMBUS_BASE_ADDRESS and enable it */
smbus_common_init();
}

View File

@ -147,7 +147,7 @@ void mainboard_romstage_entry(void)
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* Program PCH init */
pch_init();
romstage_pch_init();
ps = pmc_get_power_state();
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);