soc/intel/skylake: Rename pch_init() code
This patch renames pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot soraka successfully. Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -44,6 +44,6 @@ void bootblock_soc_init(void)
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* and abase, i2c programming and print platform info
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*/
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report_platform_info();
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pch_init();
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bootblock_pch_init();
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gspi_early_bar_init();
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}
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@ -146,7 +146,7 @@ void pch_early_iorange_init(void)
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pch_enable_lpc();
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}
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void pch_init(void)
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
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@ -24,7 +24,7 @@ void bootblock_pch_early_init(void);
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/* Bootblock post console init programming */
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void i2c_early_init(void);
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void pch_init(void);
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void bootblock_pch_init(void);
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void pch_early_iorange_init(void);
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void report_platform_info(void);
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void report_memory_config(void);
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@ -21,7 +21,7 @@
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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void systemagent_early_init(void);
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void pch_init(void);
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void romstage_pch_init(void);
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int smbus_read_byte(unsigned int device, unsigned int address);
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/* Board type */
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enum board_type {
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@ -17,11 +17,11 @@
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#include <intelblocks/tco.h>
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#include <soc/romstage.h>
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void pch_init(void)
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void romstage_pch_init(void)
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{
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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/* Program TCO_BASE_ADDRESS and TCO Timer Halt */
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tco_configure();
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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/* Program SMBUS_BASE_ADDRESS and enable it */
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smbus_common_init();
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}
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@ -147,7 +147,7 @@ void mainboard_romstage_entry(void)
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program PCH init */
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pch_init();
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romstage_pch_init();
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ps = pmc_get_power_state();
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s3wake = pmc_fill_power_state(ps) == ACPI_S3;
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fsp_memory_init(s3wake);
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