intel/common/block: Provide RAPL and min clock ratio switches in common

There are two APL specific config switches for RAPL and min. cpu clock
(APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches
could be used in future in other CPU platforms. Move them to common code
instead of having them just for one SOC.

Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings
(MSR0x610) do not change with this patch applied on mc_apl{1,4,5}
mainboard.

Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig

@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select RX6110SA_DISABLE_ACPI
 	select DRIVER_SIEMENS_NC_FPGA
 	select NC_FPGA_NOTIFY_CB_READY
-	select APL_SKIP_SET_POWER_LIMITS
+	select SOC_INTEL_DISABLE_POWER_LIMITS
 	select DRIVERS_I2C_PTN3460
 
 endif # BOARD_SIEMENS_MC_APL1

src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig

@@ -8,6 +8,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select RX6110SA_DISABLE_ACPI
 	select DRIVER_SIEMENS_NC_FPGA
 	select NC_FPGA_NOTIFY_CB_READY
-	select APL_SKIP_SET_POWER_LIMITS
+	select SOC_INTEL_DISABLE_POWER_LIMITS
 
 endif # BOARD_SIEMENS_MC_APL3

src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig

@@ -4,7 +4,7 @@ if BOARD_SIEMENS_MC_APL4
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select DRIVER_INTEL_I210
-	select APL_SET_MIN_CLOCK_RATIO
+	select SOC_INTEL_SET_MIN_CLOCK_RATIO
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select TPM_ON_FAST_SPI

src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig

@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select RX6110SA_DISABLE_ACPI
 	select DRIVER_SIEMENS_NC_FPGA
 	select NC_FPGA_NOTIFY_CB_READY
-	select APL_SKIP_SET_POWER_LIMITS
+	select SOC_INTEL_DISABLE_POWER_LIMITS
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select TPM_ON_FAST_SPI

src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig

@@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select RX6110SA_DISABLE_ACPI
 	select DRIVER_SIEMENS_NC_FPGA
 	select NC_FPGA_NOTIFY_CB_READY
-	select APL_SKIP_SET_POWER_LIMITS
+	select SOC_INTEL_DISABLE_POWER_LIMITS
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
 	select TPM_ON_FAST_SPI

src/soc/intel/apollolake/Kconfig

@@ -347,25 +347,6 @@ config CONSOLE_UART_BASE_ADDRESS
 	default 0xddffc000
 	depends on INTEL_LPSS_UART_FOR_CONSOLE
 
-config APL_SKIP_SET_POWER_LIMITS
-	bool
-	default n
-	help
-	  Some Apollo Lake mainboards do not need the Running Average Power
-	  Limits (RAPL) algorithm for a constant power management.
-	  Set this config option to skip the RAPL configuration.
-
-config APL_SET_MIN_CLOCK_RATIO
-	bool
-	depends on !APL_SKIP_SET_POWER_LIMITS
-	default n
-	help
-	  If the power budget of the mainboard is limited, it can be useful to
-	  limit the CPU power dissipation at the cost of performance by setting
-	  the lowest possible CPU clock. Enable this option if you need smallest
-	  possible CPU clock. This setting can be overruled by the OS if it has an
-	  p-state driver which can adjust the clock to its need.
-
 # M and N divisor values for clock frequency configuration.
 # These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL

src/soc/intel/apollolake/chip.c

@@ -321,7 +321,7 @@ static void soc_init(void *data)
 	 */
 	p2sb_unhide();
 
-	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
+	if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) {
 		printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
 	} else {
 		config = config_of_soc();

src/soc/intel/apollolake/cpu.c

@@ -79,11 +79,11 @@ void soc_core_init(struct device *cpu)
 	enable_pm_timer_emulation();
 
 	/* Set Max Non-Turbo ratio if RAPL is disabled. */
-	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
+	if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) {
 		cpu_set_p_state_to_max_non_turbo_ratio();
 		/* Disable speed step */
 		cpu_set_eist(false);
-	} else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) {
+	} else if (CONFIG(SOC_INTEL_SET_MIN_CLOCK_RATIO)) {
 		cpu_set_p_state_to_min_clock_ratio();
 		/* Disable speed step */
 		cpu_set_eist(false);

src/soc/intel/common/block/cpu/Kconfig

@@ -136,3 +136,21 @@ config SOC_INTEL_NO_BOOTGUARD_MSR
 	help
 	  Select this on platforms that do not support Bootguard related MSRs
 	  0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO.
+
+config SOC_INTEL_DISABLE_POWER_LIMITS
+	bool
+	default n
+	help
+	  Select this if the Running Average Power Limits (RAPL) algorithm
+	  for constant power management is not needed.
+
+config SOC_INTEL_SET_MIN_CLOCK_RATIO
+	bool
+	depends on !SOC_INTEL_DISABLE_POWER_LIMITS
+	default n
+	help
+	  If the power budget of the mainboard is limited, it can be useful to
+	  limit the CPU power dissipation at the cost of performance by setting
+	  the lowest possible CPU clock. Enable this option if you need smallest
+	  possible CPU clock. This setting can be overruled by the OS if it has an
+	  p-state driver which can adjust the clock to its need.