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cpuid: Add helper function for cpuid(1) functions 

This patch introduces 3 helper function for cpuid(1) :

1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)

Above 3 helper functions are targeted to replace majority of cpuid(1)
references.

Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2018-12-10 14:11:35 +05:30
parent e3110b8620
commit 53b08c347f
21 changed files with 142 additions and 86 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/cpu.c
View File

@ -183,7 +183,7 @@ static void identify_cpu(struct device *cpu)
/* Intel-defined flags: level 0x00000001 */
if (cpuid_level >= 0x00000001)
cpu->device = cpuid_eax(0x00000001);
cpu->device = cpu_get_cpuid();
else
/* Have CPUID level 0 only unheard of */
cpu->device = 0x00000400;

27
src/arch/x86/cpu_common.c
View File

@ -66,3 +66,30 @@ int cpu_phys_address_size(void)
return 36;
return 32;
}
/*
* Get processor id using cpuid eax=1
* return value in EAX register
*/
uint32_t cpu_get_cpuid(void)
{
return cpuid_eax(1);
}
/*
* Get processor feature flag using cpuid eax=1
* return value in ECX register
*/
uint32_t cpu_get_feature_flags_ecx(void)
{
return cpuid_ecx(1);
}
/*
* Get processor feature flag using cpuid eax=1
* return value in EDX register
*/
uint32_t cpu_get_feature_flags_edx(void)
{
return cpuid_edx(1);
}

18
src/arch/x86/include/arch/cpu.h
View File

@ -311,4 +311,22 @@ void late_car_teardown(void);
#endif
/*
* Get processor id using cpuid eax=1
* return value in EAX register
*/
uint32_t cpu_get_cpuid(void);
/*
* Get processor feature flag using cpuid eax=1
* return value in ECX register
*/
uint32_t cpu_get_feature_flags_ecx(void);
/*
* Get processor feature flag using cpuid eax=1
* return value in EDX register
*/
uint32_t cpu_get_feature_flags_edx(void);
#endif /* ARCH_CPU_H */

6
src/arch/x86/mpspec.c
View File

@ -161,14 +161,12 @@ void smp_write_processors(struct mp_config_table *mc)
unsigned int apic_version;
unsigned int cpu_features;
unsigned int cpu_feature_flags;
struct cpuid_result result;
struct device *cpu;
boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
cpu_features = result.eax;
cpu_feature_flags = result.edx;
cpu_features = cpu_get_cpuid();
cpu_feature_flags = cpu_get_feature_flags_edx();
/* order the output of the cpus to fix a bug in kernel 2.6.11 */
for (order_id = 0; order_id < 256; order_id++) {
for (cpu = all_devices; cpu; cpu = cpu->next) {

9
src/cpu/intel/common/common_init.c
View File

@ -16,20 +16,21 @@
*/
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include "common.h"
void set_vmx(void)
{
struct cpuid_result regs;
msr_t msr;
uint32_t feature_flag;
int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
int lock = IS_ENABLED(CONFIG_SET_VMX_LOCK_BIT);
regs = cpuid(1);
feature_flag = cpu_get_feature_flags_ecx();
/* Check that the VMX is supported before reading or writing the MSR. */
if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) {
if (!((feature_flag & CPUID_VMX) || (feature_flag & CPUID_SMX))) {
printk(BIOS_DEBUG, "CPU doesn't support VMX; exiting\n");
return;
}
@ -52,7 +53,7 @@ void set_vmx(void)
if (enable) {
msr.lo |= (1 << 2);
if (regs.ecx & CPUID_SMX)
if (feature_flag & CPUID_SMX)
msr.lo |= (1 << 1);
}

6
src/cpu/intel/haswell/haswell_init.c
View File

@ -606,12 +606,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
cpuid_regs = cpuid(1);
if (cpuid_regs.ecx & (1 << 18)) {
feature_flag = cpu_get_feature_flags_ecx();
if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);

21
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@ -19,6 +19,7 @@
#include <device/device.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
@ -362,12 +363,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
cpuid_regs = cpuid(1);
if (cpuid_regs.ecx & (1 << 18)) {
feature_flag = cpu_get_feature_flags_ecx();
if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);
@ -505,9 +506,9 @@ static void intel_cores_init(struct device *cpu)
static void model_206ax_report(void)
{
static const char *const mode[] = {"NOT ", ""};
struct cpuid_result cpuidr;
char processor_name[49];
int vt, txt, aes;
uint32_t cpu_id, cpu_feature_flag;
/* Print processor name */
fill_processor_name(processor_name);
@ -517,11 +518,13 @@ static void model_206ax_report(void)
printk(BIOS_INFO, "CPU: platform id %x\n", get_platform_id());
/* CPUID and features */
cpuidr = cpuid(1);
printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpuidr.eax);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
cpu_id = cpu_get_cpuid();
printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id);
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]);
printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]);
printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]);

2
src/include/cpu/x86/msr.h
View File

@ -22,6 +22,8 @@
#define SMRR_ENABLE (1 << 3)
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define CPUID_DCA (1 << 18)
#define CPUID_AES (1 << 25)
#define SGX_GLOBAL_ENABLE (1 << 18)
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define IA32_BIOS_UPDT_TRIG 0x79

15
src/northbridge/intel/haswell/report_platform.c
View File

@ -24,7 +24,7 @@
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
u32 i, index;
u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@ -51,12 +51,15 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpu_id,
microcode_ver.hi, cpu_name);
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
}

8
src/northbridge/intel/sandybridge/raminit.c
View File

@ -19,6 +19,7 @@
#include <commonlib/region.h>
#include <bootmode.h>
#include <string.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <cbmem.h>
#include <halt.h>
@ -287,7 +288,6 @@ static void init_dram_ddr3(int min_tck, int s3resume)
spd_raw_data spds[4];
struct region_device rdev;
ramctr_timing *ctrl_cached;
struct cpuid_result cpures;
int err;
u32 cpu;
@ -369,8 +369,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
ctrl.tCK = min_tck;
/* Get architecture */
cpures = cpuid(1);
cpu = cpures.eax;
cpu = cpu_get_cpuid();
ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Get DDR3 SPD data */
@ -391,8 +390,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
ctrl.tCK = min_tck;
/* Get architecture */
cpures = cpuid(1);
cpu = cpures.eax;
cpu = cpu_get_cpuid();
ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Reset DDR3 frequency */

9
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -17,6 +17,7 @@
#include <console/console.h>
#include <string.h>
#include <arch/cpu.h>
#include <arch/io.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <device/pci_def.h>
@ -190,14 +191,12 @@ void dram_xover(ramctr_timing * ctrl)
static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
{
struct cpuid_result cpures;
u32 addr, cpu, stretch;
stretch = ctrl->ref_card_offset[channel];
/* ODT stretch: Delay ODT signal by stretch value.
* Useful for multi DIMM setups on the same channel. */
cpures = cpuid(1);
cpu = cpures.eax;
cpu = cpu_get_cpuid();
if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
if (stretch == 2)
stretch = 3;
@ -3020,11 +3019,9 @@ void set_scrambling_seed(ramctr_timing * ctrl)
void set_4f8c(void)
{
struct cpuid_result cpures;
u32 cpu;
cpures = cpuid(1);
cpu = (cpures.eax);
cpu = cpu_get_cpuid();
if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
MCHBAR32(0x4f8c) = 0x141D1519;
} else {

7
src/soc/intel/broadwell/cpu.c
View File

@ -19,6 +19,7 @@
#include <device/pci.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
@ -498,12 +499,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
cpuid_regs = cpuid(1);
if (cpuid_regs.ecx & (1 << 18)) {
feature_flag = cpu_get_feature_flags_ecx();
if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);

15
src/soc/intel/broadwell/romstage/report_platform.c
View File

@ -86,7 +86,7 @@ static struct {
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
u32 i, index;
u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@ -114,12 +114,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
if (cpu_table[i].cpuid == cpuidr.eax) {
if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@ -127,11 +127,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
cpuidr.eax, cpu_type, microcode_ver.hi);
cpu_id, cpu_type, microcode_ver.hi);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
"VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
}

15
src/soc/intel/cannonlake/bootblock/report_platform.c
View File

@ -96,7 +96,7 @@ static uint16_t get_dev_id(pci_devfn_t dev)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
u32 i, index;
u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@ -128,12 +128,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
if (cpu_table[i].cpuid == cpuidr.eax) {
if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@ -141,11 +141,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
cpuidr.eax, cpu_type, microcode_ver.hi);
cpu_id, cpu_type, microcode_ver.hi);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);

7
src/soc/intel/cannonlake/cpu.c
View File

@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci.h>
#include <chip.h>
@ -104,12 +105,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
cpuid_regs = cpuid(1);
if (cpuid_regs.ecx & (1 << 18)) {
feature_flag = cpu_get_feature_flags_ecx();
if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);

8
src/soc/intel/common/block/vmx/vmx.c
View File

@ -11,8 +11,10 @@
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/msr.h>
#include <intelblocks/vmx.h>
#include <soc/cpu.h>
@ -46,11 +48,11 @@ static int soc_vmx_enabled(void)
void vmx_configure(void *unused)
{
msr_t msr;
struct cpuid_result regs;
uint32_t feature_flag;
regs = cpuid(1);
feature_flag = cpu_get_feature_flags_ecx();
if (!soc_vmx_enabled() || !(regs.ecx & CPUID_VMX)) {
if (!soc_vmx_enabled() || !(feature_flag & CPUID_VMX)) {
printk(BIOS_ERR, "VMX: pre-conditions not met\n");
return;
}

15
src/soc/intel/icelake/bootblock/report_platform.c
View File

@ -92,7 +92,7 @@ static uint16_t get_dev_id(pci_devfn_t dev)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
u32 i, index;
u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@ -124,12 +124,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
if (cpu_table[i].cpuid == cpuidr.eax) {
if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@ -137,11 +137,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
cpuidr.eax, cpu_type, microcode_ver.hi);
cpu_id, cpu_type, microcode_ver.hi);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);

7
src/soc/intel/icelake/cpu.c
View File

@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci.h>
#include <chip.h>
@ -105,12 +106,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
cpuid_regs = cpuid(1);
if (cpuid_regs.ecx & (1 << 18)) {
feature_flag = cpu_get_feature_flags_ecx();
if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);

9
src/soc/intel/quark/romstage/report_platform.c
View File

@ -67,14 +67,13 @@ static uint32_t fuse_port_read(uint32_t offset)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
const char *cpu_type = "Unknown";
u32 d_variant;
u32 ecc_enabled;
u32 extended_temp;
u32 i;
u8 revision;
u32 secure_boot;
u32 secure_boot, cpu_id;
const char *stepping = "Unknown";
/* Determine if ECC is enabled */
@ -94,9 +93,9 @@ static void report_cpu_info(void)
extended_temp = 0;
/* Look for string to match the CPU ID value */
cpuidr = cpuid(1);
cpu_id = cpu_get_cpuid();
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
if ((cpu_table[i].cpuid == cpuidr.eax)
if ((cpu_table[i].cpuid == cpu_id)
&& (cpu_table[i].extended_temp == extended_temp)
&& (cpu_table[i].ecc == ecc_enabled)
&& (cpu_table[i].secure_boot == secure_boot)
@ -118,7 +117,7 @@ static void report_cpu_info(void)
}
}
printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpuidr.eax,
printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpu_id,
revision, cpu_type, stepping);
}

15
src/soc/intel/skylake/bootblock/report_platform.c
View File

@ -121,7 +121,7 @@ static uint16_t get_dev_id(pci_devfn_t dev)
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
u32 i, index;
u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@ -149,12 +149,12 @@ static void report_cpu_info(void)
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
if (cpu_table[i].cpuid == cpuidr.eax) {
if (cpu_table[i].cpuid == cpu_id) {
cpu_type = cpu_table[i].name;
break;
}
@ -162,11 +162,12 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
cpuidr.eax, cpu_type, microcode_ver.hi);
cpu_id, cpu_type, microcode_ver.hi);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
cpu_feature_flag = cpu_get_feature_flags_ecx();
aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);

7
src/soc/intel/skylake/cpu.c
View File

@ -16,6 +16,7 @@
*/
#include <assert.h>
#include <arch/cpu.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
@ -333,12 +334,12 @@ static void enable_lapic_tpr(void)
static void configure_dca_cap(void)
{
struct cpuid_result cpuid_regs;
uint32_t feature_flag;
msr_t msr;
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
cpuid_regs = cpuid(1);
if (cpuid_regs.ecx & (1 << 18)) {
feature_flag = cpu_get_feature_flags_ecx();
if (feature_flag & CPUID_DCA) {
msr = rdmsr(IA32_PLATFORM_DCA_CAP);
msr.lo |= 1;
wrmsr(IA32_PLATFORM_DCA_CAP, msr);