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drop some unused files and fix warnings on i945 based systems. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-22 11:50:52 +00:00 committed by Stefan Reinauer
parent c02b4fc9db
commit 53b0ea4bf2
40 changed files with 76 additions and 311 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/i386/Makefile.inc
View File

@ -139,6 +139,9 @@ endif
ifeq ($(CONFIG_CPU_AMD_SOCKET_940),y)
crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
endif
ifeq ($(CONFIG_CPU_INTEL_ATOM_230),y)
crt0s += $(src)/cpu/intel/model_106cx/cache_as_ram.inc
endif
ifeq ($(CONFIG_CPU_INTEL_CORE),y)
crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
endif
@ -199,8 +202,9 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)
$(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
printf " GEN romstage.inc\n"
printf " CC romstage.inc\n"
$(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -include $(obj)/build.h -I$(src) -I. -c -S $< -o $@.tmp1
printf " POST romstage.inc\n"
sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $@.tmp1 > $@.tmp
mv $@.tmp $@
rm -f $@.tmp1

2
src/cpu/Kconfig
View File

@ -10,11 +10,9 @@ config USE_DCACHE_RAM
config DCACHE_RAM_BASE
hex
default 0xffdf8000 if CPU_INTEL_CORE
config DCACHE_RAM_SIZE
hex
default 0x8000 if CPU_INTEL_CORE
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex

6
src/cpu/intel/model_106cx/cache_as_ram_disable.c
View File

@ -19,6 +19,10 @@
#include "cpu/x86/car/copy_and_run.c"
/* called from assembler code */
void stage1_main(unsigned long bist);
/* from romstage.c */
void real_main(unsigned long bist);
void stage1_main(unsigned long bist)
@ -39,8 +43,6 @@ void stage1_main(unsigned long bist)
printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
}
cpu_reset_x:
printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
if(cpu_reset == 0) {

6
src/cpu/intel/model_6ex/cache_as_ram_disable.c
View File

@ -21,6 +21,10 @@
#include "cpu/x86/car/copy_and_run.c"
/* called from assembler code */
void stage1_main(unsigned long bist);
/* from romstage.c */
void real_main(unsigned long bist);
void stage1_main(unsigned long bist)
@ -40,8 +44,6 @@ void stage1_main(unsigned long bist)
printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
#endif
cpu_reset_x:
printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
printk(BIOS_SPEW, "No cache as ram now - ");

9
src/mainboard/intel/d945gclf/Kconfig
View File

@ -20,17 +20,21 @@
config BOARD_INTEL_D945GCLF
bool "D945GCLF"
select ARCH_X86
select CPU_INTEL_CORE
select CPU_INTEL_ATOM_230
select CPU_INTEL_SOCKET_441
select NORTHBRIDGE_INTEL_I945
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_SMSC_LPC47M15X
select BOARD_HAS_FADT
select GENERATE_ACPI_TABLES
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select USE_PRINTK_IN_CAR
select AP_IN_SIPI_WAIT
@ -38,6 +42,9 @@ config BOARD_INTEL_D945GCLF
select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_512
select USE_DCACHE_RAM
select GFXUMA
select TINY_BOOTBLOCK
config MAINBOARD_DIR
string

30
src/mainboard/intel/d945gclf/acpi_tables.c
View File

@ -32,6 +32,7 @@
#define OLD_ACPI 0
extern unsigned char AmlCode[];
void *amlcodeptr = &AmlCode;
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
@ -65,17 +66,10 @@ typedef struct acpi_oemb {
} __attribute__((packed)) acpi_oemb_t;
#endif
typedef struct acpi_gnvs {
// 0x00
u16 osys;
u8 smif;
u8 reserved[13];
// 0x10
u8 mpen;
} __attribute__((packed)) acpi_gnvs_t;
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
#if OLD_ACPI
void acpi_create_oemb(acpi_oemb_t *oemb)
static void acpi_create_oemb(acpi_oemb_t *oemb)
{
acpi_header_t *header = &(oemb->header);
unsigned long tolud;
@ -114,13 +108,14 @@ void acpi_create_oemb(acpi_oemb_t *oemb)
};
#endif
void acpi_create_gnvs(acpi_gnvs_t *gnvs)
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->mpen = 1;
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
}
void acpi_create_intel_hpet(acpi_hpet_t * hpet)
static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
{
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header);
@ -212,7 +207,6 @@ unsigned long write_acpi_tables(unsigned long start)
#if OLD_ACPI
acpi_oemb_t *oemb;
#endif
acpi_gnvs_t *gnvs;
acpi_header_t *ssdt;
acpi_header_t *dsdt;
@ -279,10 +273,10 @@ unsigned long write_acpi_tables(unsigned long start)
ALIGN_CURRENT;
acpi_create_facs(facs);
int len = ((acpi_header_t *) amlcodeptr)->length;
dsdt = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode)->length;
memcpy((void *) dsdt, (void *) AmlCode,
((acpi_header_t *) AmlCode)->length);
current += len;
memcpy((void *) dsdt, amlcodeptr, len);
#if OLD_ACPI
for (i=0; i < dsdt->length; i++) {
@ -299,14 +293,14 @@ unsigned long write_acpi_tables(unsigned long start)
/* Pack GNVS into the ACPI table area */
for (i=0; i < dsdt->length; i++) {
if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, current);
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
break;
}
}
/* And fill it */
acpi_create_gnvs(current);
acpi_create_gnvs((global_nvs_t *)current);
current += 0x100;
ALIGN_CURRENT;

3
src/mainboard/intel/d945gclf/mainboard.c
View File

@ -20,10 +20,9 @@
#include <device/device.h>
#include <console/console.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
#include "chip.h"
int add_northbridge_resources(struct lb_memory *mem);
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);

1
src/mainboard/intel/d945gclf/mainboard_smi.c
View File

@ -20,6 +20,7 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
/* The southbridge SMI handler checks whether gnvs has a

2
src/mainboard/intel/d945gclf/mptable.c
View File

@ -25,7 +25,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";

8
src/mainboard/intel/d945gclf/romstage.c
View File

@ -83,7 +83,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/reset_test.c"
#include "northbridge/intel/i945/errata.c"
#include "northbridge/intel/i945/debug.c"
@ -216,8 +215,6 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
#include "southbridge/intel/i82801gx/cmos_failover.c"
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
@ -228,6 +225,8 @@ static void early_ich7_init(void)
//
#include "lib/cbmem.c"
#include "cpu/intel/model_106cx/cache_as_ram_disable.c"
void real_main(unsigned long bist)
{
u32 reg32;
@ -337,7 +336,7 @@ void real_main(unsigned long bist)
* day.
*/
if (resume_backup_memory)
memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
@ -345,4 +344,3 @@ void real_main(unsigned long bist)
#endif
}
#include "cpu/intel/model_106cx/cache_as_ram_disable.c"

2
src/mainboard/intel/eagleheights/romstage.c
View File

@ -121,8 +121,6 @@ static inline int spd_read_byte(u16 device, u8 address)
#include "northbridge/intel/i3100/reset_test.c"
#include "debug.c"
#include "southbridge/intel/i3100/cmos_failover.c"
void early_config(void) {
device_t dev;
u32 gcs, rpc, fd;

7
src/mainboard/kontron/986lcd-m/acpi_tables.c
View File

@ -30,6 +30,7 @@
#include "dmi.h"
extern unsigned char AmlCode[];
void *amlcodeptr = &AmlCode;
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
@ -203,10 +204,10 @@ unsigned long write_acpi_tables(unsigned long start)
ALIGN_CURRENT;
acpi_create_facs(facs);
int len = ((acpi_header_t *) amlcodeptr)->length;
dsdt = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode)->length;
memcpy((void *) dsdt, (void *) AmlCode,
((acpi_header_t *) AmlCode)->length);
current += len;
memcpy((void *) dsdt, amlcodeptr, len);
ALIGN_CURRENT;

3
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -91,7 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/reset_test.c"
#include "northbridge/intel/i945/errata.c"
#include "northbridge/intel/i945/debug.c"
@ -352,8 +351,6 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
#include "southbridge/intel/i82801gx/cmos_failover.c"
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol

13
src/mainboard/roda/rk886ex/acpi_tables.c
View File

@ -31,13 +31,14 @@
#include "dmi.h"
extern unsigned char AmlCode[];
void *amlcodeptr = &AmlCode;
#if CONFIG_HAVE_ACPI_SLIC
unsigned long acpi_create_slic(unsigned long current);
#endif
#define OLD_ACPI 0
#if OLD_ACPI
void acpi_create_gnvs(global_nvs_t *gnvs)
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset (gnvs, 0, sizeof(global_nvs_t));
@ -91,7 +92,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
#endif
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
void acpi_create_gnvs(global_nvs_t *gnvs)
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
@ -110,7 +111,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->did[4] = 0x00000005;
}
void acpi_create_intel_hpet(acpi_hpet_t * hpet)
static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
{
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header);
@ -272,10 +273,10 @@ unsigned long write_acpi_tables(unsigned long start)
ALIGN_CURRENT;
acpi_create_facs(facs);
int len = ((acpi_header_t *)amlcodeptr)->length;
current += len;
dsdt = (acpi_header_t *) current;
current += ((acpi_header_t *) AmlCode)->length;
memcpy((void *) dsdt, (void *) AmlCode,
((acpi_header_t *) AmlCode)->length);
memcpy((void *) dsdt, amlcodeptr, len);
/* Fix up global NVS region for SMI handler. The GNVS region lives
* in the (high) table area. The low memory map looks like this:

1
src/mainboard/roda/rk886ex/m3885.c
View File

@ -275,7 +275,6 @@ void m3885_configure_multikey(void)
maxvars = m3885_get_variable(0x00);
printk(BIOS_DEBUG, "M388x has %d variables in original bank.\n", maxvars);
for (i=0; i<ARRAY_SIZE(variables); i+=3) {
u8 reg8;
if(variables[i + 0] > maxvars)
continue;
reg8 = m3885_get_variable(variables[i + 0]);

3
src/mainboard/roda/rk886ex/mainboard.c
View File

@ -27,6 +27,7 @@
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
#include <arch/coreboot_tables.h>
#include "chip.h"
#include "ec.h"
@ -133,8 +134,6 @@ static void mainboard_enable(device_t dev)
#endif
}
int add_northbridge_resources(struct lb_memory *mem);
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);

1
src/mainboard/roda/rk886ex/mainboard_smi.c
View File

@ -22,6 +22,7 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "../../../southbridge/intel/i82801gx/i82801gx_nvs.h"
/* The southbridge SMI handler checks whether gnvs has a

2
src/mainboard/roda/rk886ex/mptable.c
View File

@ -27,7 +27,7 @@
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";

8
src/mainboard/roda/rk886ex/romstage.c
View File

@ -79,9 +79,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/reset_test.c"
#include "northbridge/intel/i945/errata.c"
#include "northbridge/intel/i945/debug.c"
@ -259,8 +259,6 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
#include "southbridge/intel/i82801gx/cmos_failover.c"
static void init_artec_dongle(void)
{
// Enable 4MB decoding
@ -277,6 +275,7 @@ static void init_artec_dongle(void)
// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"
void real_main(unsigned long bist)
{
@ -391,7 +390,7 @@ void real_main(unsigned long bist)
* day.
*/
if (resume_backup_memory)
memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
/* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
@ -399,4 +398,3 @@ void real_main(unsigned long bist)
#endif
}
#include "cpu/intel/model_6ex/cache_as_ram_disable.c"

10
src/northbridge/intel/i945/debug.c
View File

@ -23,7 +23,7 @@
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
static void print_pci_devices(void)
static inline void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@ -42,7 +42,7 @@ static void print_pci_devices(void)
}
}
static void dump_pci_device(unsigned dev)
static inline void dump_pci_device(unsigned dev)
{
int i;
@ -61,7 +61,7 @@ static void dump_pci_device(unsigned dev)
}
}
static void dump_pci_devices(void)
static inline void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@ -78,7 +78,7 @@ static void dump_pci_devices(void)
}
}
void dump_spd_registers(void)
static inline void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
@ -103,7 +103,7 @@ void dump_spd_registers(void)
}
}
static void dump_mem(unsigned start, unsigned end)
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");

2
src/northbridge/intel/i945/errata.c
View File

@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "raminit.h"
int fixup_i945_errata(void)
{
u32 reg32;

3
src/northbridge/intel/i945/raminit.c
View File

@ -199,6 +199,8 @@ static int sdram_capabilities_two_dimms_per_channel(void)
return (reg8 != 0);
}
// TODO check if we ever need this function
#if 0
static int sdram_capabilities_MEM4G_disable(void)
{
u8 reg8;
@ -208,6 +210,7 @@ static int sdram_capabilities_MEM4G_disable(void)
return (reg8 != 0);
}
#endif
#define GFX_FREQUENCY_CAP_166MHZ 0x04
#define GFX_FREQUENCY_CAP_200MHZ 0x03

4
src/northbridge/intel/i945/raminit.h
View File

@ -68,5 +68,7 @@ struct sys_info {
} __attribute__ ((packed));
void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path);
unsigned long get_top_of_ram(void);
int fixup_i945_errata(void);
#endif /* RAMINIT_H */

28
src/northbridge/intel/i945/reset_test.c
View File

@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static int bios_reset_detected(void)
{
/* For now ...
* DO NOT, I repeat, DO NOT remove this. If you don't like the
* situation, implement this instead.
*/
return 0;
}

6
src/pc80/mc146818rtc_early.c
View File

@ -57,14 +57,14 @@ static int cmos_chksum_valid(void)
}
static int last_boot_normal(void)
static inline int last_boot_normal(void)
{
unsigned char byte;
byte = cmos_read(RTC_BOOT_BYTE);
return (byte & (1 << 1));
}
static int do_normal_boot(void)
static inline int do_normal_boot(void)
{
unsigned char byte;
@ -107,7 +107,7 @@ static int do_normal_boot(void)
return (byte & (1<<1));
}
static unsigned read_option(unsigned start, unsigned size, unsigned def)
static inline unsigned read_option(unsigned start, unsigned size, unsigned def)
{
#if CONFIG_USE_OPTION_TABLE == 1
unsigned byte;

35
src/southbridge/intel/i3100/cmos_failover.c
View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i3100.h"
#define RTC_FAILED (1 <<2)
#define GEN_PMCON_3 0xa4
static void check_cmos_failed(void)
{
u8 byte;
byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (byte & RTC_FAILED) {
// clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

2
src/southbridge/intel/i82801ax/Makefile.inc
View File

@ -32,7 +32,5 @@ driver-y += i82801ax_usb_ehci.o
obj-y += i82801ax_reset.o
obj-y += i82801ax_watchdog.o
# TODO: What about cmos_failover.c?
# TODO: Fix and enable i82801ax_smbus.o later.

32
src/southbridge/intel/i82801ax/cmos_failover.c
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i82801ax.h"
static void check_cmos_failed(void)
{
uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (byte & RTC_FAILED) {
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

2
src/southbridge/intel/i82801bx/Makefile.inc
View File

@ -32,7 +32,5 @@ driver-y += i82801bx_usb_ehci.o
obj-y += i82801bx_reset.o
obj-y += i82801bx_watchdog.o
# TODO: What about cmos_failover.c?
# TODO: Fix and enable i82801bx_smbus.o later.

32
src/southbridge/intel/i82801bx/cmos_failover.c
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i82801bx.h"
static void check_cmos_failed(void)
{
uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (byte & RTC_FAILED) {
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

19
src/southbridge/intel/i82801cx/cmos_failover.c
View File

@ -1,19 +0,0 @@
//kind of cmos_err for ich3
#include "i82801cx.h"
static void check_cmos_failed(void)
{
#if CONFIG_HAVE_OPTION_TABLE
uint8_t byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
if( byte & RTC_BATTERY_DEAD) {
// Set boot_option and last_boot to 'Fallback',
// clear reboot_bits
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
#endif
}

35
src/southbridge/intel/i82801dx/cmos_failover.c
View File

@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Ron G. Minnich
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// kind of cmos_err for ICH4
#define RTC_FAILED (1 <<2)
#define GEN_PMCON_3 0xa4
static void check_cmos_failed(void)
{
u8 byte;
byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (byte & RTC_FAILED) {
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

16
src/southbridge/intel/i82801ex/cmos_failover.c
View File

@ -1,16 +0,0 @@
//kind of cmos_err for ich5
#define RTC_FAILED (1 <<2)
#define GEN_PMCON_3 0xa4
static void check_cmos_failed(void)
{
uint8_t byte;
byte = pci_read_config8(PCI_DEV(0,0x1f,0),GEN_PMCON_3);
if( byte & RTC_FAILED){
//clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

36
src/southbridge/intel/i82801gx/cmos_failover.c
View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* (C) 2008-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "i82801gx.h"
#define RTC_FAILED (1 << 2)
#define GEN_PMCON_3 0xa4
static void check_cmos_failed(void)
{
u8 byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (byte & RTC_FAILED) {
// clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
byte &= 0x0c;
byte |= CONFIG_MAX_REBOOT_CNT << 4;
cmos_write(byte, RTC_BOOT_BYTE);
}
}

4
src/southbridge/ti/pci7420/pci7420_cardbus.c
View File

@ -83,12 +83,12 @@ static void pci7420_cardbus_init(device_t dev)
#endif
}
void pci7420_cardbus_read_resources(device_t dev)
static void pci7420_cardbus_read_resources(device_t dev)
{
cardbus_read_resources(dev);
}
void pci7420_cardbus_set_resources(device_t dev)
static void pci7420_cardbus_set_resources(device_t dev)
{
printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev));

2
src/southbridge/ti/pci7420/pci7420_firewire.c
View File

@ -30,8 +30,6 @@
static void pci7420_firewire_init(device_t dev)
{
u8 reg8;
printk(BIOS_DEBUG, "TI PCI7420/7620 FireWire init\n");
#ifdef ODD_IRQ_FIXUP

1
src/superio/renesas/m3885x/superio.c
View File

@ -29,7 +29,6 @@
#include <stdlib.h>
#include "chip.h"
void set_kbc_ps2_mode(void);
void m3885_configure_multikey(void);
static void m3885x_init(device_t dev)

2
src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
View File

@ -34,7 +34,7 @@ static void pnp_exit_conf_state(device_t dev)
outb(0xaa, port);
}
static void lpc47b272_enable_serial(device_t dev, unsigned iobase)
static inline void lpc47b272_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

1
src/superio/smsc/lpc47m15x/superio.c
View File

@ -41,7 +41,6 @@ static void lpc47m15x_init(device_t dev);
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
static void dump_pnp_device(device_t dev);
struct chip_operations superio_smsc_lpc47m15x_ops = {
CHIP_NAME("SMSC LPC47M15x/192/997 Super I/O")

2
src/superio/winbond/w83627thg/w83627thg_early_serial.c
View File

@ -36,7 +36,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
outb(0xaa, port);
}
static void w83627thg_enable_serial(device_t dev, unsigned int iobase)
static inline void w83627thg_enable_serial(device_t dev, unsigned int iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);